TLK10081 Datasheet, PDF (7/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

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TERMINAL
SIGNAL
BGA
M8
J6
PRTAD[4:0]
L9
G9
E10
RESET_N
H5
MDC
J8
MDIO
J7
TDI
C8
TDO
D6
TMS
B8
TCK
D8
TRST_N
E5
TESTEN
L10
GPI0
J10
GPI1
M9
AMUXA
C11
AMUXB
D4
TLK10081
SLLSEE9 – NOVEMBER 2013
Table 2-1. Pin Description - Signal Pins (continued)
DIRECTION
TYPE
SUPPLY
Input
LVCMOS
1.5V/1.8V
VDDO[1:0]
DESCRIPTION
MDIO Port Address. Used to select the MDIO port address.
The TLK10081 will respond if the port address field on MDIO protocol (PA[4:0]) matches
PRTAD[4:0].)
Input
LVCMOS
1.5V/1.8V
VDDO01
Input
LVCMOS
with Hysteresis
1.5V/1.8V
VDDO1
Input/Output
LVCMOS
1.5V/1.8V
VDDO1
25Ω Driver
Input LVCMOS
1.5V/1.8V VDDO0
(Internal Pullup)
Output LVCMOS
1.5V/1.8V VDDO0
50Ω Driver
Input LVCMOS
1.5V/1.8V VDDO0
(Internal Pullup)
Input LVCMOS
with Hysteresis
1.5V/1.8V VDDO0
Input LVCMOS
1.5V/1.8V VDDO0
(Internal Pulldown)
Input LVCMOS
1.5V/1.8V VDDO1
Input LVCMOS
1.5V/1.8V VDDO1
Input LVCMOS
1.5V/1.8V VDDO1
Analog I/O
Analog I/O
Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10µs after
device power stabilization.
MDIO Clock Input. Clock input for the Clause 22 MDIO interface.
Note that an external pullup is generally not required on MDC.
MDIO Data I/O. MDIO interface data input/output signal for the Clause 22 MDIO interface. This
signal must be externally pulled up to VDDO using a 2kΩ resistor.
During device reset (RESET_N asserted low) this pin is floating. During software initiated power
down the management interface remains active for control register writes and reads. Certain
status bits are not deterministic as their generating clock source may be disabled as a result of
asserting either power down input signal. During pin based power down (PDTRXA_N and
PDTRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted
high both channels), this pin is driven normally.
JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during
the operation of the test port. In system applications where JTAG is not implemented, this input
signal may be left floating.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled
up. During register based power down, (1.15 asserted high both channels), this pin is pulled up
normally.
JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device
during the operation of the test port. When the test port is not in use, TDO is in a high impedance
state.
During device reset (RESET_N asserted low) this pin is floating. During pin based power down
(PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During register based power
down, (1.15 asserted high both channels), this pin is pulled up normally.
JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system
applications where JTAG is not implemented, this input signal can be left unconnected.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled
up. During register based power down, (1.15 aserted high both channels), this pin is pulled up
normally.
JTAG Clock. TCK is used to clock state information and test data into and out of the device
during boundary scan operation. In system applications where JTAG is not implemented, this
input signal should be grounded.
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This
input can be left unconnected in the application and is pulled down internally, disabling the JTAG
circuitry. If JTAG is implemented on the application board, this signal should be deasserted (high)
during JTAG system testing, and otherwise asserted (low) during normal operation mode.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled
down. During register based power down (1.15 asserted high both channels), this pin is pulled
down normally.
Test Enable. This signal is used during the device manufacturing process. It should be grounded
through a resistor in the device application board.
General Purpose Input Zero. This signal is used during the device manufacturing process. It
should be grounded through a resistor on the device application board.
General Purpose Input One. This signal is used during the device manufacturing process. It
should be grounded through a resistor on the device application board.
SERDES Channel A Analog Testability I/O. This signal is used during the device manufacturing
process. It should be left unconnected in the device application.
SERDES Channel B Analog Testability I/O. This signal is used during the device manufacturing
process. It should be left unconnected in the device application.
Copyright © 2013, Texas Instruments Incorporated
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