TLK10081 Datasheet, PDF (16/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
3.4.6 Power Down Mode
The TLK10081 can be put in power down either through device inputs pins or through MDIO control
register (1.15). PDTRXA_N: Active low, powers down the channel.
The MDIO management serial interface remains operational when in register based power down mode
(1.15 asserted for both channels), but status bits may not be valid since the clocks are disabled. The low
speed side and high speed side SERDES outputs are high impedance when in power down mode. Please
see the detailed per pin description for the behavior of each device I/O signal during pin based and
register based power down.
3.4.7 Transmit / Receive Latency
The latency through the TLK10081 is shown in Figure 3-7. Note that the latency ranges shown indicate
static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is
initially established. During normal operation, the latency through the device is fixed.
Figure 3-7. TLK10081 Transmit / Receive Latency
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FUNCTIONAL DESCRIPTION
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