TLK10081 Datasheet, PDF (42/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
Table 6-36. LS_CH_CONTROL_1
Register Address:0x1C SPACER Default: 0x0000
Bit(s) Name
Description
15
RESERVED
For TI use only (Default 1’b0)
14:12 LS_RXFIFO_DEPTH_SEL[2:0] RX FIFO depth select (Default 3’b000)
11:10 LS_RXFIFO_WMK_SEL[1:0]
RX FIFO Water mark select (Default 2’b00)
9
RX_GIGE_EN
0 = Disable GIGE mode on receive path (Default 1’b0)
1 = Enable GIGE mode on receive path
8
TX_GIGE_EN
0 = Disable GIGE mode on transmit path (Default 1’b0)
1 = Enable GIGE mode on transmit path
7:6
RESERVED
For TI use only (Default 2’b00)
5
LS_CHSYNC_FORCE_SYNC Lane can be selected in LS_SERDES_CONTROL_1.
0 = Keep byte alignment determined by ch sync state machine (Default 1’b0)
1 = Force byte alignment to 9 unless LS_CHSYNC_JOG_EN is 1
4
RESERVED
For TI use only (Default 1'b0)
3
LS_ENC_BYPASS
1 = Disables Encoder on LS side on selected lane.
0 = Normal operation (1’b0)
2
LS_DEC_BYPASS
1 = Disables Decoder on LS side on selected lane.
0 = Normal operation (1’b0)
1:0
LS_CH_SYNC_HYS_SEL[1:0] LS Channel synchronization hysteresis selection for selected lane. Lane can be
selected in LS_SERDES_CONTROL_1.
00 = The channel synchronization, when in the synchronization state, performs
the Ethernet standard specified hysteresis to return to the LOS state (Default
2’b00)
01 = A single 8b/10b invalid decode error or disparity error causes the channel
synchronization state machine to immediately transition from sync to LOS
10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the
channel synchronization state machine to immediately transition from sync to LOS
11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause the
channel synchronization state machine to immediately transition from sync to LOS
Access
RW/SC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 6-37. HS_CH_CONTROL_1
Register Address:0x1D SPACER Default: 0x0880
Bit(s) Name
Description
15
RESERVED
For TI use only (Default 1’b0)
14:12 HS_RXFIFO_DEPTH_SEL[2:0]
FIFO depth select for both HS RX0/RX1 FIFO’s (Default 3’b000)
11
RX_LANE_MARKER_EN
Marker enable control on receive side (Default 1’b1)
0 = Normal operation
1 = Enable marker search/replacement. Marker search/replacement character
RW can be selected in VS_RX_MARKER_SEARCH_CHARACTER
(0x8002.9:0), VS_RX_MARKER_REPLACE_CHARACTER (0x8003.9:0)
10:8 HS_TXFIFO_DEPTH_SEL[2:0]
HS TX FIFO depth select
7
TX_LANE_MARKER_EN
Marker enable control on transmit side (Default 1’b1)
0 = Normal operation
1 = Enable marker search/replacement. Marker search/replacement character
RW can be selected in VS_TX_MARKER_SEARCH_CHARACTER
(0x8000.9:0), VS_TX_MARKER_REPLACE_CHARACTER (0x8001.9:0)
6
RESERVED
For TI use only (Default 1’b0)
5
HS_CHSYNC_FORCE_SYNC
0 = Keep byte alignment determined by ch sync state machine (Default 1’b0)
1 = Force byte alignment to 9 unless HS_CHSYNC_JOG_EN is 1
4
HS_CHSYNC_JOG_EN
0 = Disable manual jog function (Default 1’b0)
1 = Enable manual jog function
3
HS_ENC_BYPASS
0 = Normal operation. (Default 1’b0)
1 = Disables 8B/10B encoder on HS side.
2
HS_DEC_BYPASS
0 = Normal operation. (Default 1’b0)
1 = Disables 8B/10B decoder on HS side.
Access
RW/SC
RW
RW
RW
RW
RW
RW
RW
RW
RW
42
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