TLK10081 Datasheet, PDF (37/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
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SLLSEE9 – NOVEMBER 2013
Table 6-25. CHANNEL_STATUS_1 (continued)
Register Address:0x0F SPACER Default:0x0000
Bit(s) Name
Description
0
HS_PLL_LOCK
HS Serdes PLL lock indicator
When high, indicates HS Serdes PLL achieved lock to the selected incoming
REFCLK0/1_P/N
Access
RO/LL
Table 6-26. HS_ERROR_COUNTER
Register Address:0x10 SPACER Default:0xFFFD
Bit(s) Name
Description
15:0 HS_ERR_COUNT[15:0]
In functional mode, this counter reflects number of invalid code words (includes
disparity errors) received by decoder.
In HS test pattern verification mode , this counter reflects error count for the test
pattern selected through 11.10:8
When PRBS_EN pin is set, this counter reflects error count for selected PRBS
pattern. Counter value cleared to 16’h0000 when read.
Access
COR
Table 6-27. LS_LN_ERROR_COUNTER
Register Address:0x11 SPACER Default:0xFFFD
Bit(s) Name
Description
15:0 LS_LN_ERR_COUNT[15:0]
LS Lane Error counter. Lane can be selected through LS_LN_CFG_EN[2:0]
(6.14:12)
In functional mode, this counter reflects number of invalid code words (includes
disparity errors) received by decoder.
In LS test pattern verification mode , this counter reflects error count for the test
pattern selected through 12.10:8
Counter value cleared to 16’h0000 when read.
Access
COR
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