TLK10081 Datasheet, PDF (15/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
Note that it is possible to operate one direction (transmit or receive) of a particular channel in 1:1 mode
while the other direction operates in 8:1 mode.
3.4.2 Clock Tolerance Compensation
The phase-correction FIFOs used to interface between the low speed and high speed clock domains
within the device are also capable of clock tolerance compensation (CTC). If enabled, the CTC function
will correct for clock rate mismatches by periodically inserting or deleting a user-defined reserved “idle”
character. Note that character insertion only occurs immediately following detection of an existing “idle”
character, so these should occur regularly in the data stream to ensure that compensation can be
performed frequently enough to avoid FIFO collisions.
3.4.3 Crosspoint Switch
The TLK10081’s default lane ordering passes through low speed input lanes (0 through 7) into fixed
positions in the outputted high speed aggregate link. The high speed receiver will then identify which
positions correspond to which lanes and output them accordingly on its low speed outputs. However, it is
possible to reconfigure the data sources that are associated with each output lane/position through MDIO.
For each HS transmit output, the source can be selected from the low speed input of the same channel or
from either channel's high speed input. For the LS transmit output, data can be sourced from the low
speed input or either channel's high speed input.Since the data source (input) assigned to each output is
configured independently, a broadcast/fan-out function can be supported.
3.4.4 Unused Lanes
Some lanes may not be used all the time. When they are disconnected, data stuffing must occur to fill in
the void left by the missing input data. In TLK10081, the data pattern sent to represent lane down should
not alias with actual data; therefore, a repeated fill data sequence is used. The active/not active status of
all lanes can be monitored through MDIO.
To implement the lane down function on the RX side, eight separate state machines will monitor the high
speed data for the fill sequence and indicate the status of each lane through the low speed status register
0x13.
3.4.5 Test Pattern Generationa and Verification
The TLK10081 has an extensive suite of built in test functions to support system diagnostic requirements.
Each channel has sets of internal test pattern generators and verifiers.
Several patterns can be selected via the MDIO interface that offer extensive test coverage. The low speed
side supports generation and verification of pseudo-random bit sequence (PRBS) 2⁷-1, 2²³-1, and 2³¹-1
patterns. In addition to those PRBS patterns, the high speed side supports High-frequency (HF), Low-
frequency (LF), Mixed-frequency (MF), and continuous random test pattern (CRPAT) long/short pattern
generation and verification as defined in IEEE Standard 802.3.
The TLK10081 provides two pins: PRBSEN and PRBS_PASS, for additional and easy control and
monitoring of PRBS pattern generation and verification. When the PRBSEN is asserted high, the internal
PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed
and low speed sides of both channels. This signal is logically OR’d with an MDIO register bits A.13:12 and
B.13:12.
PRBS 2³¹-1 is selected by default, and can be changed through MDIO.
When PRBS test is enabled (PRBSEN=1):
PRBS_PASS=1 indicates that PRBS pattern reception is error free.
PRBS_PASS=0 indicates that a PRBS error is detected. The channel, the side (high speed or low speed),
and the lane (for low speed side) that this signal refers to is chosen through MDIO register bit 0.3:0.
Copyright © 2013, Texas Instruments Incorporated
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FUNCTIONAL DESCRIPTION
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