TLK10081 Datasheet, PDF (17/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
4 SERDES INTERFACES
SLLSEE9 – NOVEMBER 2013
4.1 High Speed CML Output
The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up
resistors, requiring no external components. The transmit outputs must be AC coupled.
HSTXAP
HSTXAN
50 ohm transmission line
50 ohm transmission line
HSRXAP
50
50
GND
V_TERM
HSRXAN
TRANSMITTER
MEDIA
RECEIVER
Figure 4-1. Example of High Speed I/O AC Coupled Mode (Channel A HS side is shown)
Current Mode Logic (CML) drivers often require external components. The disadvantage of the external
component is a limited edge rate due to package and line parasitic. The CML driver on TLK10081 has on-
chip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased speed
requirements. The transmitter output driver is highly configurable allowing output amplitude and de-
emphasis to be tuned to a channel's individual requirements. Software programmability allows for very
flexible output amplitude control. Only AC coupled output mode is supported.
When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal
is attenuated due to the skin effect of the media. This causes a “smearing” of the data eye when viewed
on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In
order to provide equalization for the high frequency loss, 4-tap finite impulse response (FIR) transmit de-
emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by
allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. Output
swing control is via MDIO.
See Figure 7-2 for output waveform flexibility. The level of de-emphasis is programmable via the MDIO
interface through control registers (5.7:4 and 5.12:8) through pre-cursor and post-cursor settings. Users
can control the strength of the de-emphasis to optimize for a specific system requirement.
4.2 High Speed Receiver
The high speed receiver is differential CML with internal termination resistors. The receiver requires AC
coupling. The termination impedances of the receivers are configured as 100 Ohms with the center tap
weakly tied to 0.8*VDDT with a capacitor to create an AC ground.
TLK10081 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion
loss by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both the gain and bandwidth of the
equalizer are controlled by the receiver equalization logic.
4.3 Loss of Signal Output Generation (LOS)
Loss of input signal detection is based on the voltage level of each serial input signal INA*P/N,
HSRXAP/N, and HSRXBP/N. Anytime the serial receive input differential signal peak to peak voltage level
is ≤75 mV_pp for High Speed side or ≤ 65mV_pp for Low Speed side, LOSA or LOSB are asserted (high true)
respectively for Channel A and Channel B (if enabled, disabled by default). Note that an input signal ≥ 150
mV_pp for High Speed side and ≥ 175 mV_pp for Low Speed side is required for reliable operation of the loss
of signal detection circuits. If the input signal is between these two ranges, the SERDES will operate
properly, but the LOS indication will not be valid (or robust). The LOS indications are also directly readable
through the MDIO interface in respective registers.
Copyright © 2013, Texas Instruments Incorporated
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SERDES INTERFACES
17