TLK10081 Datasheet, PDF (5/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
2.3 Terminal Functions
The details of the terminal functions of the TLK10081 device are provided in Table 2-1 and Table 2-2.
Table 2-1. Pin Description - Signal Pins
TERMINAL
SIGNAL
BGA
CHANNEL A
HSTXAP
D12
HSTXAN
E12
HSRXAP
HSRXAN
INA[7:0]P/N
OUTA[7:0]P/N
B12
A12
M3/M4
L1/M1
K2/L2
H1/J1
D1/E1
B2/C2
A1/B1
A4/A3
M7/M6
L6/L5
K5/K4
J3/H3
F3/E3
C4/C5
B5/B6
A6/A7
DIRECTION
TYPE
SUPPLY
Output
CML
VDDA_HS
Input
CML
VDDA_HS
Input
CML
VDDA_LS
Output
CML
VDDA_LS
LOSA
Output LVCMOS
E9
1.5V/1.8V
VDDO0
40Ω Driver
RXCTRL_0
Input
B10
LVCMOS
1.5V/1.8V
VDDO0
GPO0
Output
LVCMOS
D9
1.5V/1.8V
VDDO0
40Ω Driver
Input
PDTRXA_N
A8
LVCMOS
1.5V/1.8V
VDDO0
CHANNEL B (High Speed Interface Only)
HSTXBP
HSTXBN
K12
L12
Output
CML
VDDA_HS
HSRXBP
HSRXBN
H12
G12
Input
CML
VDDA_HS
DESCRIPTION
High Speed Transmit Channel A Output. HSTXAP and HSTXAN comprise the high speed side
transmit direction Channel A differential serial output signal. During device reset (RESET_N
asserted low) these pins are driven differential zero. These CML outputs must be AC coupled.
High Speed Receive Channel A Input. HSRXAP and HSRXAN comprise the high speed side
receive direction Channel A differential serial input signal. These CML input signals must be AC
coupled.
Low Speed Channel A Inputs. INAP and INAN comprise the low speed side transmit direction
differential input signals. These signals must be AC coupled.
Low Speed Channel A Outputs. OUTAP and OUTAN comprise the low speed side receive
direction differential output signals. During device reset (RESET_N asserted low) these pins are
driven differential zero. These signals must be AC coupled.
Channel A Receive Loss Of Signal (LOS) Indicator.
LOSA=0: Signal detected.
LOSA=1: Loss of signal.
Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential
input signal swing of ≤75 mV_pp, LOSA will be asserted (if enabled). If the input signal is greater
than 150 mV_p-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined.
Other functions can be observed on LOSA real-time, configured via MDIO
During device reset (RESET_N asserted low) this pin is driven low. During pin based power down
(PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is
floating.
It is highly recommended that LOSA be brought to an easily accessible point on the application
board (header) in the event that debug is required.
Channel A Bit Interleave Lane Rotation Jog.
A toggle of this pin, either from high to low or from low to high, causes a lane rotation of the
HSRXAP/N source data.
Channel A Multi-purpose Status Indicator.
This pin should be left unconnected in the device application.
Transceiver Power Down.
When this pin is held low (asserted), the device is placed in power down mode. When deasserted,
the device operates normally. After deassertion, a software data path reset should be issued
through the MDIO interface.
Serial Transmit Channel B Output. HSTXBP and HSTXBN comprise the high speed side
transmit direction Channel B differential serial output signal. During device reset (RESET_N
asserted low) these pins are driven differential zero. These CML outputs must be AC coupled.
Serial Receive Channel B Input. HSRXBP and HSRXBN comprise the high speed side receive
direction Channel B differential serial input signal. These CML input signals must be AC coupled.
Copyright © 2013, Texas Instruments Incorporated
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