TLK10081 Datasheet, PDF (29/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
Table 6-7. HS_SERDES_CONTROL_3
Register Address:0x04 SPACER Default:0x1500
Bit(s)
Name
Description
15
HS_ENTRACK
HSRX ADC Track mode.
0 = Normal operation (Default 1’b0)
1 = Forces ADC into track mode
14:12
HS_EQPRE[2:0]
Serdes Rx precursor equalizer selection
000 = 1/9 cursor amplitude
001 = 3/9 cursor amplitude (Default 3’b001)
010 = 5/9 cursor amplitude
011 = 7/9 cursor amplitude
100 = 9/9 cursor amplitude
101 =11/9 cursor amplitude
110 = 13/9 cursor amplitude
111 = Disable
11:10
HS_CDRFMULT[:10]
Clock data recovery algorithm frequency multiplication selection (Default 2'b01)
00 = First order. Frequency offset tracking disabled
01 = Second order. 1x mode
10 = Second order. 2x mode
11 = Reserved
9:8
HS_CDRTHR[1:0]
Clock data recovery algorithm threshold selection (Default 2'b01)
00 = Four vote threshold
01 = Eight vote threshold
10 = Sixteen vote threshold
11 = Thirty two vote threshold
7
RESERVED
For TI use only (Default 1’b0)
6
HS_PEAK_DISABLE HS Serdes PEAK_DISABLE control
0 = Normal operation (Default 1’b0)
1 = Disables high frequency peaking. Suitable for <6 Gbps operation
5
HS_H1CDRMODE
HS_Serdes H1CDRMODE control
0 = Normal operation (Default 1’b0)
1 = Enables CDR mode suitable for short channel operation.
4:0
HS_TWCRF[4:0]
Cursor Reduction Factor (Default 5’b00000). Refer to Table 6-8.
Access
RW
RW
RW
RW
RW
RW
RW
RW
Table 6-8. HSTX Cursor Reduction Factor Weights
VALUE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
4.4:0
CURSOR REDUCTION
(%)
0
2.5
5.0
7.5
10.0
12
15
Reserved
VALUE
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
4.4:0
CURSOR REDUCTION
(%)
17
20
22
25
27
30
32
35
37
40
42
45
47
50
52
55
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