English
Language : 

TLK10081 Datasheet, PDF (14/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR
TLK10081
SLLSEE9 – NOVEMBER 2013
10-Bit Programmable byte
boundary framer
A4 A3 A2 A1
1.25Gbps
B5 B4 B3 B2
1.25Gbps
C4 C3 C2 C1
2.5Gbps
1.25Gbps
D5 D4 D3 D2
1.25Gbps
E6 E5 E4 E3
1.25Gbps
F3 F2 F1 F0
1.25Gbps
G7 G6 G5 G4
1.25Gbps
H5 H4 H3 H2
1.25Gbps
TLK10081 TX
CH
A2 A1
SYNC
FIFO + A2
Marker M0
B3 B2
CH
SYNC
B3
FIFO
B2
C2 C1
CH
SYNC
D3 D2
CH
SYNC
CH
E4 E3
SYNC
F1 F0
CH
SYNC
C2
FIFO
C1
FIFO
FIFO
D3
D2
M
U
X
E4
E3
F1
FIFO
F0
G5 G4
CH
SYNC
H3 H2
CH
SYNC
G5
FIFO
G4
H3
FIFO
H2
10-Bit Programmable Marker
Replacement
A1
M0
MARKER
REPLACE +
LANE
ORDERING
TLK10081 RX
A2
FIFO
A1
SKEW A2 A1
B3
FIFO
B2
SKEW B3 B2
10Gbps
H2 G4 F0 E3 D2 C1 B2 M0
C2
FIFO
C1
C2 C1
SKEW
CH
SYNC
D3
D
FIFO
E D2
M
U
X E4
FIFO
E3
D3 D2
SKEW
SKEW E4 E3
F1
FIFO
F0
SKEW F1 F0
G5
FIFO
G4
G5 G4
SKEW
H3
FIFO
H2
SKEW H3 H2
www.ti.com
10-Bit Programmable Marker ID
and Replacement
M0
A1
1.25Gbps
A4 A3 A2 A1
1.25Gbps
B5 B4 B3 B2
1.25Gbps
C4 C3 C2 C1
1.25Gbps
D5 D4 D3 D2
1.25Gbps
E6 E5 E4 E3
1.25Gbps
F3 F2 F1 F0
1.25Gbps
G7 G6 G5 G4
1.25Gbps
H5 H4 H3 H2
Sn Symbol ± 10 bits
M0 Lane 0 Marker ± 10 bits ± Programmable char identified is replaced with programmable Marker
Figure 3-5. Block Diagram of the Interleave/De-interleave Scheme
3.4 Additional Functionality
3.4.1 1:1 Mode
The TLK10081 also supports a 1:1 mode for data retiming. The data path for this mode is shown below. In
the transmit direction, data is received by the low-speed deserializer on Lane 0 of the selected channel,
aligned to word boundaries (if applicable), 8b/10b decoded (if applicable), input to a phase-correction
FIFO capable of clock tolerance compensation, optionally 8b/10b encoded, and transmitted out the high
speed serial ports. The receive direction operates similarly, but in the opposite direction (eventually
outputting the serial data on low speed Lane 0).
Ch_sync
JOG
1:1 Mode TX
8b/10b
Decoder
FIFO
8b/10b
Encoder
8b/10b
Encoder
1:1 Mode RX
FIFO
8b/10b
Decoder
Ch_sync
JOG
Figure 3-6. 1:1 Mode Datapath
14
FUNCTIONAL DESCRIPTION
Submit Documentation Feedback
Product Folder Links: TLK10081
Copyright © 2013, Texas Instruments Incorporated