TLK10081 Datasheet, PDF (22/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
6 PROGRAMMERS REFERENCE
PRTAD[4:0] determine the device port address. In this mode, TLK10081 will respond if the PHY address
field on the MDIO protocol (PA[4:0]) matches PRTAD[4:0] pin value).
6.1 MDIO Management Interface
The TLK10081 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK10081 is possible without use of this interface. However, some
features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The port address is determined by control pins PRTAD[4:0] as described in Table 2-1).
In Clause 22, the control pins PRTAD[4:0] determine the device port address.
TLK10081 will respond if the 5 bits of PHY address field on MDIO protocol (PA[4:0] match PRTAD[4:0]).
The MACRO_ACCESS bit in Register 0x00 determines which high speed channel/port within the
TLK10081 is controlled by the high speed registers. A value of 0 selects High Speed Channel A and 1
selects High Speed Channel B. The GLOBAL_WRITE bit can be set to 1 to apply the same settings to
both high speed channels.
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register will return a 0.
MDIO Protocol Timing:The Clause 22 timing required to read from the internal registers is shown in
Figure 6-1. The Clause 22 timing required to write to the internal registers is shown in Figure 6-2.
MDC
MDIO
0
1
1
0
PA[4:0]
RA4 RA0 Z
0 D15 D0 ¹
> 32 "1's"
Preamble
Start
Read
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK10081.
Figure 6-1. CL22 - Management Interface Read Timing
MDC
MDIO
0
1
0
1
PA[4:0]
RA4 RA0 1
0 D15 D0 ¹
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 6-2. CL22 - Management Interface Write Timing
Clause 22 Indirect Addressing:The TLK10081 Register space is divided into two register groups. One
register group can be addressed directly through Clause 22, and one register group can be addressed
indirectly through Clause 22. The register group which can be addressed through Clause 22 indirectly is
implemented in vendor specific register space (16’h8000 onwards). Due to clause 22 register space
limitations, an indirect addressing method is implemented so that this extended register space can be
accessed through clause 22. To access this register space (16’h8000 onwards), an address control
register (Reg 30, 5’h1E) should be written with the register address followed by a read/write transaction to
address data register (Reg 31, 5’h1F) to access the contents of the address specified in address control
register.
22
PROGRAMMERS REFERENCE
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