TLK10081 Datasheet, PDF (32/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
VALUE
0011
0100
0101
0110
0111
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Table 6-14. LS PLL Multiplier Control (continued)
6.3:0
PLL MULTIPLIER FACTOR
Reserved
8x
10x
12x
12.5x
VALUE
1011
1100
1101
1110
1111
6.3:0
PLL MULTIPLIER FACTOR
Reserved
Reserved
50x
65x
Reserved
Table 6-15. LS_SERDES_CONTROL_2
Register Address:0x07 SPACER Default:0xDD05
Bit(s)
Name
Description
15
RESERVED
For TI use only.
14:12
LS_SWING[2:0]
Output swing control on LS Serdes side. (Default 3’b101)
Refer to Table 6-16.
11
LS_LOS
LS Serdes LOS detector control
0 = Disable Loss of signal detection on LS serdes lane inputs
1 = Enable Loss of signal detection on LS serdes lane inputs (Default 1’b1)
10
LS_TX_ENRX
LS Serdes enable control on the transmit channel. LS Serdes per lane on transmitter
channel is automatically disabled when PD_TRXx_N is asserted LOW or when
register bit 1.15 is set HIGH.
0 = Disables LS serdes lane
1 = Enables LS serdes lane (Default 1’b1)
9:8
LS_TX_RATE [1:0] LS Serdes lane rate settings on transmit channel.
00 = Full rate
01 = Half rate (Default 2’b01)
10 = Quarter rate
11 = Reserved
7:4
LS_DE[3:0]
LS Serdes De-emphasis settings. (Default 4’b0000)
3
RESERVED
For TI use only .
2
LS_RX_ENTX
LS Serdes lane enable control on receive channel. LS Serdes per lane on receiver
channel is automatically disabled when PD_TRXx_N is asserted LOW or when
register bit 1.15 is set HIGH.
0 = Disables LS serdes lane
1 = Enables LS serdes lane (Default 1’b1)
1:0
LS_RX_RATE [1:0] LS Serdes lane rate settings on receive channel.
00 = Full rate
01 = Half rate (Default 2’b01)
10 = Quarter rate
11 = Reserved
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 6-16. LSRX Output AC Mode Output Swing Control
VALUE
7.14:12
000
001
010
011
100
101
110
111
AC MODE
TYPICAL AMPLITUDE (mVdfpp)
190
380
560
710
850
950
1010
1050
32
PROGRAMMERS REFERENCE
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