TLK10081 Datasheet, PDF (11/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

www.ti.com
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
TLK10081 TX
Read
Controlle
r
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
M
U
LN0
X _MARK
FIFO
TLK10081
SLLSEE9 – NOVEMBER 2013
M
U 8b/10b
X
M
U
X
M
U
SCR
X
M
U 8b/10b
X
M
U
X
M
U
SCR
X
Figure 3-2. Transmit Datapath, Raw Serial Data (Bit Interleave)
3.2 Receive (De-Interleaving) Direction
With the device configured to operate in the normal transceiver (mission) mode, the receive data paths are
as shown in Figure 3-2, Receive data path (10-bit mode), and Figure 3-3, Receive data path (raw serial
mode).
In the receive direction, the high speed aggregate stream is received by a deserializer capable of data
rates up to 10 Gbps. The deserialized data is then aligned to 20-bit boundaries by the device’s channel
synchronization logic. This alignment can be based on a user-defined 10-bit alignment code (in the case
of 8b/10b or otherwise 10-bit delineated data) or can be done arbitrarily (for cases where 10-bit delineation
is not meaningful). In either case, the chosen word boundaries can be adjusted manually if necessary to
adjust the bit assignments.
Once the data is aligned, it can be optionally 8b/10b decoded or descrambled as needed before being
input to the device’s receive lane ordering logic (discussed in detail in Section 3.3). After lane assignments
are determined, the de-aggregated serial data streams are input to independent FIFOs in order to absorb
phase variations between the high-speed and low-speed clock domains and to compensate for clock rate
differences if desired.
Each low speed data stream will pass through a programmable skew buffer (in case delays need to be
added to certain lanes in order to meet system-level skew requirements) and optionally 8b/10b encoded
before being output by a serializer capable of rates up to 1.25 Gbps.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK10081
FUNCTIONAL DESCRIPTION
11