TLK10081 Datasheet, PDF (40/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
Table 6-31. SKEW_CONFIG_CONTROL (continued)
Register Address:0x16 SPACER Default:0x0000
Bit(s)
Name
Description
6:4
RX0_SKEW_CONFIG[2:0] Skew config for lanes 0-3 on receive path (Default 3’b000)
000 - No Skew
001 - Align lanes 0,1
010 - Align lanes 0,1,2
X11- Align lanes 0,1,2,3
100 - Align lanes 2,3
101 - Align lanes 0,1 and 2,3
110 - Reserved
2:0
TX0_SKEW_CONFIG[2:0] Skew config for lanes 0-3 on transmit path (Default 3’b000)
000 - No Skew
001 - Align lanes 0,1
010 - Align lanes 0,1,2
X11- Align lanes 0,1,2,3
100 - Align lanes 2,3
101 - Align lanes 0,1 and 2,3
110 - Reserved
Table 6-32. HS_ALIGN_CODE_CONTROL
Register Address:0x17 SPACER Default:0x02BC
Bit(s)
Name
Description
15
RESERVED
For TI use only (Default 1’b0)
14:12
TX_LANE_MARKER[2:0]
Marker selection on transmit side (Default 3’b000)
11
BIT_LM_EN
0 = Normal operation (Default 1’b0)
1 = Enable lane marker generation in selected LS TX lane through
TX_LANE_MARKER
When set to 1, lane marker message is generated (CRC field set to
32’hFE00_00FE).
When LS_LM_EN and LS_LOS_EN are set to 1, lane marker message is
generated.
10:0
RESERVED
For TI use only (Default 11’h2BC)
Table 6-33. BIT_LM_CONTROL
Register Address:0x18 SPACER Default:0x0CC8
Bit(s)
Name
Description
15
RESERVED
For TI use only (Default 1’b0)
14:12
RX_LANE_MARKER[2:0]
Marker selection on receive side (Default 3’b000)
11
BIT_LM_PATT_DETECT_EN Applicable only when RX_BIT_INTERLEAVE is set to 1.
0 = Normal operation
1 = Enable marker detection (Default 1’b1)
10:0
RESERVED
For TI use only (Default 11’h4C8)
Table 6-34. LS_TXFIFO_CONTROL
Register Address:0x19 SPACER Default:0x02BC
Bit(s)
Name
Description
15:13
LS_TXFIFO_DEPTH_SEL[2:0]
TX FIFO depth select (Default 3’b000)
12:11
LS_TXFFIO_WMK_SEL[1:0]
TX FIFO Water mark select (Default 2’b00)
10
LS_CHSYNC_ALIGN_CODE_ EN Lane can be selected in LS_SERDES_CONTROL_1.
0 = Normal operation (Default 1’b0)
1 = Use align code specified in LS_CH_SYNC_ALIGN_CODE in LS ch
sync SM
9:0
LS_CHSYNC_ALIGN_CODE[ 9:0] Lane can be selected in LS_SERDES_CONTROL_1.
10 bit align code to use when LS_CHSYNC_ALIGN_CODE_EN is set
(Default 10’h2BC)
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