TLK10081 Datasheet, PDF (25/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
Table 6-1. GLOBAL_CONTROL_1⁽¹⁾
Register Address:0x00 SPACER Default: 0x0610
Bit(s) Name
Description
15
GLOBAL_RESET
Global reset.
0 = Normal operation (Default 1’b0)
1 = Resets TX and RX data path including MDIO registers. Equivalent to asserting
RESET_N.
14:13
RESERVED
For TI use only. Always reads 0.
12
MACRO_ACCESS
0 = Access HS/LT Control/status specific to HS macro A (Default 1’b0)
1 = Access HS /LT Control/status specific to alternate HS macro
11
GLOBAL_WRITE
0 = HS/LT Control settings are applied to HS macro specified in MACRO_ACCESS
(Default 1’b0)
1 = HS/LT Control settings are applied to both HS 0/1 macros
10:7
RESERVED
For TI use only (Default 4’b1100)
6:5
RESERVED
For TI use only. Always reads 0.
4:0
PRBS_PASS_OVERLAY[4:0] PRBS_PASS pin status selection. Applicable only when PRBS test pattern
verification is enabled on HS side or LS side.
PRBS_PASS pin reflects PRBS verification status on selected HS macro/ LS lane
1xx00 = PRBS_PASS reflects combined status of Macro A/B HS serdes PRBS
verification. If PRBS verification fails on any channel HS serdes, PRBS_PASS will be
asserted low. (Default 5’b10000)
00000 = Status from macro A HS Serdes side
00001 = Reserved status from macro A HS core side
0001x = Reserved
00100 = Status from LS Serdes side Lane 0
00101 = Status from LS Serdes side Lane 1
00110 = Status from LS Serdes side Lane 2
00111 = Status from LS Serdes side Lane 3
01000 = Status from macro B HS Serdes side
01001 = Reserved
0101x = Reserved
01100 = Status from LS Serdes side Lane 4
01101 = Status from LS Serdes side Lane 5
01110 = Status from LS Serdes side Lane 6
01111 = Status from LS Serdes side Lane 7
(1) This global register is channel independent.
(2) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
Access
RW
SC ⁽²⁾
RW
RW
RW
RW
RW
RW
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