TLK10081 Datasheet, PDF (26/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
Table 6-2. CHANNEL_CONTROL_1
Register Address:0x01 SPACER Default: 0x4000
Bit(s) Name
Description
15
POWERDOWN
Setting this bit high powers down entire data path with exception that MDIO interface stays
active.
0 = Normal operation (Default 1’b0)
1 = Power Down mode is enabled.
14
LT_ENABLE
1 = Enable link training (Default 1’b1)
0 = Disable link training
This bit should be set to HIGH for auto train mode to function correctly
13:10 RESERVED
For TI use only (Default 4’b0000)
9
RX_BIT_INTERLEAVE 0 = Normal operation. (Default 1’b0)
1 = Enable bit interleave on receive path
8
TX_BIT_INTERLEAVE 0 = Normal operation. (Default 1’b0)
1 = Enable bit interleave on transmit path
7:4
RESERVED
For TI use only (Default 4’b0000)
3
RX_1LN_MODE_SEL 0 = Enable 8ln mode on receive path(Default 1’b0)
1 = Enable 1ln mode on receive datapath
2
TX_1LN_MODE_SEL 1 = Enable 8ln mode on transmit datapath(Default 1’b0)
1 = Enable 1ln mode on transmit datapath
1
REFCLK_SW_SEL
Channel HS Reference clock selection. Applicable only when REFCLK_SEL pin is LOW.
0 = Selects REFCLK_0_P/N as clock reference to HS side serdes macro x (Default 1’b0)
1 = Selects REFCLK_1_P/N as clock reference to HS side serdes macro x
0
LS_REFCLK_SEL
Channel LS Reference clock selection.
0 = LS side serdes reference clock is same as HS side serdes reference clock (E.g. If
REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_0_P/N is
selected as LS side serdes reference clock and vice versa) (Default 1’b0)
1 = Alternate reference clock is selected as clock reference to LS side serdes (E.g. If
REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_1_P/N is
selected as LS side serdes reference clock and vice versa)
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 6-3. HS_SERDES_CONTROL_1
Register Address:0x02 SPACER Default: 0x831D
Bit(s) Name
Description
15:10 RESERVED
For TI use only (Default 6’b100000)
9:8
HS_LOOP_BANDWIDTH[1:0] HS Serdes PLL Loop Bandwidth settings
00 = Medium Bandwidth
01 = Low Bandwidth
10 = High Bandwidth
11 = Ultra High Bandwidth. (Default 2'b11)
7
RESERVED
For TI use only (Default 1’b0)
6
HS_VRANGE
HS Serdes PLL VCO range selection.
0 = VCO runs at higher end of frequency range (Default 1’b0)
1 = VCO runs at lower end of frequency range
This bit needs to be set HIGH if VCO frequency (REFCLK *HS_PLL_MULT) is below
2.5 GHz.
5
RESERVED
For TI use only (Default 1’b0)
4
HS_ENPLL
HS Serdes PLL enable control. HS Serdes PLL is automatically disabled when
PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.
0 = Disables PLL in HS serdes
1 = Enables PLL in HS serdes (Default 1’b1)
3:0
HS_PLL_MULT[3:0]
HS Serdes PLL multiplier setting (Default 4’b1101).
Refer to Table 6-4
Access
RW
RW
RW
RW
RW
RW
RW
26
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