TLK10081 Datasheet, PDF (34/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
Table 6-20. HS_OVERLAY_CONTROL (continued)
Register Address:0x09 SPACERDefault:0x0380
Bit(s) Name
Description
6
LS_PLL_LOCK_OVERLAY 0 = LOSx pin does not reflect loss of LS SERDES PLL lock status (Default 1’b0)
1 = Allows LS SERDES loss of PLL lock status to be reflected on LOSx pin
5
HS_CH_SYNC_OVERLAY 0 = LOSx pin does not reflect receive channel loss of channel synchronization status
or loss of block lock (Default 1’b0)
1 = Allows channel loss of synchronization or loss of block lock to be reflected on
LOSx pin
4
HS_INVALID_CODE_
0 = LOSx pin does not reflect receive channel invalid code word error (Default 1’b0)
OVERLAY
1 = Allows invalid code word error to be reflected on LOSx pin
3
HS_AGCLOCK_OVERLAY 0 = LOSx pin does not reflect HS Serdes AGC unlock status (Default 1’b0)
1 = Allows HS Serdes AGC unlock status to be reflected on LOSx pin
2
HS_AZDONE_OVERLAY 0 = LOSx pin does not reflect HS Serdes auto zero calibration not done status (Default
1’b0)
1 = Allows auto zero calibration not done status to be reflected on LOSx pin
1
HS_PLL_LOCK_OVERLAY 0 = LOSx pin does not reflect loss of HS Serdes PLL lock status (Default 1’b0)
1 = Allows HS Serdes loss of PLL lock status to be reflected on LOSx pin
0
HS_LOS_OVERLAY
0 = LOSx pin does not reflect HS Serdes Loss of signal condition (Default 1’b0)
1 = Allows HS Serdes Loss of signal condition to be reflected on LOSx pin
Access
RW
RW
RW
RW
RW
RW
RW
Table 6-21. LS_TP_OVERLAY_CONTROL
Register Address:0x0A SPACER Default:0x0500
Bit(s) Name
Description
15
LS_RX_OVERSAMPLING
0 = Disable LS lane oversampling on receive path (Default 1’b0)
1 = Enable LS lane oversampling on receive path
14
LS_TX_OVERSAMPLING
0 = Disable LS lane oversampling on transmit path (Default 1’b0)
1 = Enable LS lane oversampling on transmit path
13
LS_TP_GEN_EN
0 = Normal operation (Default 1’b0)
1 = Activates test pattern generation selected by LS_TEST_PATT_SEL on the LS
side
12
LS_TP_VERIFY_EN
0 = Normal operation (Default 1’b0)
1 = Activates PRBS/CRPAT test pattern verification selected by
LS_TEST_PATT_SEL on the LS side
10:8 LS_TEST_PATT_SEL[2:0]
LS Test Pattern Selection LS_TEST_PATT_SEL[2:0]. Refer Test pattern
procedures section for more information.
000 = High Frequency Test Pattern
001 = Low Frequency Test Pattern
010 = Mixed Frequency Test Pattern
011 = CRPAT Long
100 = CRPAT Short
101, 11x = PRBS pattern selected by LS_PRBS_SEL (Default 3’b101)
Errors can be checked by reading LS_LN_ERROR_COUNT register
7
RESERVED
For TI use only (Default 1’b0)
6:4
LS_TX_LANE_DELAY
Manual delay (skew) for selected LS lane on transmit path (Default 3’b000).
Applicable only when LS_TX_LANE_DELAY_EN is set.
1 = Enable lane skew delay as specified in LS_TX_LANE_DELAY
000 = 10 bits of lane skew
001 = 20 bits of lane skew
010 = 30 bits of lane skew
011 = 40 bits of lane skew
1xx = Reserved
3
LS_TX_LANE_DELAY_EN
0 = Disable lane skew delay(Default 1’b0)
1 = Overrides any settings from TX0_SKEW_CONFIG (0x16.2:0). Enables skew
control through LS_TX_LANE_DELAY.
2
LS_CH_SYNC_OVERLAY
0 = LOSx pin does not reflect LS Serdes lane loss of synchronization condition
(Default 1’b0)
1 = Allows LS serdes lane loss of synchronization condition to be reflected on LOSx
pin
1
LS_INVALID_CODE_OVERLAY 0 = LOSx pin does not reflect LS Serdes lane invalid code condition (Default 1’b0)
1 = Allows LS serdes lane invalid code condition to be reflected on LOSx pin
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
34
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