TLK10081 Datasheet, PDF (20/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
5.1.1 Refclk Frequency Selection Example
If the low speed side line rate is 0.6Gbps, the high-speed side line rate will be 4.8Gbps. The following
steps can be taken to make a reference clock frequency selection:
1. Determine the appropriate SERDES rate modes that support the required line rates. Table 5-2 shows
that the 0.6Gbps line rate on the low speed side is only supported in the quarter rate mode (RateScale
= 2). Table 5-3 shows that the 4.8Gbps line rate on the high speed side is only supported in the half
rate mode (RateScale = 0.5).
2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding
reference clock frequencies using the formula:
Reference Clock Frequency = (LineRate x RateScale)/MPY
The computed reference clock frequencies are shown in Table 5-4 along with the valid minimum and
maximum frequency values.
3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that
fall outside the allowed range. In this example, the common frequencies are highlighted in Table 5-4 .
4. Select any of the remaining marked common reference clock frequencies. The higher the reference
clock frequency usually the better. In this example, any of the following reference clock frequencies
can be selected: 150MHz, 200MHz, 240MHz, and 300MHz.
Note that for Low Speed side rates of at least 500Mbps, a general rule to follow is that half rate on the
Low Speed side will correspond to full rate on the High Speed side, and quarter rate on the Low Speed
side will correspond to half rate on the High Speed side. And, the high speed PLL multiplier will be 2x of
low speed.
Table 5-4. Reference Clock Frequency Selection Example
LOW SPEED SIDE SERDES
SERDES PLL ^{REFERENCE CLOCK FREQUENCY (MHz)}
MULTIPLIER _COMPUTED
MIN
MAX
4
300
250
425
5
240
200
425
6
200
166.667
416.667
8
150
125
312.5
10
120
122.88
250
HIGH SPEED SIDE SERDES
SERDES PLL ^{REFERENCE CLOCK FREQUENCY (MHz)}
MULTIPLIER _COMPUTED
MIN
MAX
4
600
375
425
5
480
300
425
6
400
250
425
8
300
187.5
390.625
10
240
150
312.5
12
200
125
260.417
15
160
122.88
208.333
16
150
122.88
195.3125
20
120
122.88
156.25
5.1.2 Low Speed Side Rates Below 500Mbps
For serial links below 500Mbps, the Low Speed Side SERDES must be configured using twice the desired
data rate. For instance, 270Mbps data must be configured for 540Mbps. In addition, the device must be
configured through MDIO to run at half speed (register TBD). This enables over-sampling of data to
support data rates lower than the Low Speed side SERDES IP allows. Note that the High Speed SERDES
should be configured for the actual data rate, and not 2x. Using the same 270Mbps example, the high
speed side should be configured for 0.27x8 = 2.16Gbps.
Also note the Low Speed side and High Speed side will have the same rate, and the High Speed PLL
multiplier will be 2x of Low Speed. For 270Mbps/2.16Gbps and a REFCLK of 135Mhz, the Low Speed
side will be set to 8x, Quarter Rate (540Mhz) and the High Speed side will be set to 16x, Quarter Rate
(2.16Gbps).
20
CLOCKING
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