TLK10081 Datasheet, PDF (21/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
5.2 Clocking Architecture
A simplified clocking architecture for the TLK10081 is captured in Figure 5-1. Each channel (Channel A or
Channel B) has an option of operating with a differential reference clock provided either on pins
REFCLK0P/N or REFCLK1P/N. The choice is made either through MDIO or through REFCLK_SEL pins.
The reference clock frequencies for those two clock inputs can be different as long as they fall under the
valid ranges shown in Table 5-3. For each channel, the low speed side SERDES, high speed side
SERDES and the associated part of the digital core operate from the same reference clock.
The clock and data recovery (CDR) function of the high speed side receiver recovers the clock from the
incoming serial data. The high speed side SERDES makes available two versions of clocks for further
processing:
1. HS_RXBCLK_A/B: recovered byte clock synchronous with incoming serial data and with a frequency
matching the incoming line rate divided by 20.
2. VCO_CLOCK_A/B_DIV2: VCO frequency divided by 2. (VCO frequency = REFCLK x PLL Multiplier).
The above-mentioned clocks can be output through the differential pins, CLKOUTAP/N and
CLKOUTBP/N, with optional frequency division ratios of 1, 2, 4, 5, 8, 10, 16, 20, or 25. The clock output
options are software controlled through the MDIO interface register 0x15. The maximum CLKOUT
frequency is 500MHz.
INA[7:0]P/N
OUTA[7:0]P/N
Low
Speed
Side
SERDES
REFCLKA_SEL
+
REFCLK0P/N _{_}
+
REFCLK1P/N _{_}
REFCLKB_SEL
HS_RXBCLK_A
VCO_CLOCK_A_DIV2
High
Speed
Side
SERDES
Channel A
HSTXAP/N
HSRXAP/N
2
A S/W
Reg: 1.3:2
Reg: 1.7:4
4
Divide by N
+
(N=1,2,4,5,8,
10,16,20,25)
_
Divide by N
+
(N=1,2,4,5,8,
10,16,20,25)
_
4
2
B S/W
Reg: 1.3:2
Reg: 1.7:4
CLKOUTAP/N
CLKOUTBP/N
VCO_CLOCK_B_DIV2
HS_RXBCLK_B
High
Speed
Side
SERDES
Channel B
HSTXBP/N
HSRXBP/N
Figure 5-1. Clocking Architecture
Copyright © 2013, Texas Instruments Incorporated
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