TLK10081 Datasheet, PDF (45/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
Table 6-52. VS_TX_POLY_CONTROL_0
Register Address:0x800F SPACER Default: 0x00C0
Bit(s) Name
Description
15:0
TX_SCR_SEED[31:16]
[15:0] bits of 32 bit Tx scrambler polynomial. Bit 0 always set to 1’b0. (Default
16’h00C0).
Access
RW
Table 6-53. VS_RX_DESCR_CONTROL
Register Address:0x8019 SPACER Default: 0xFC00
Bit(s) Name
Description
15:2
RESERVED
For TI use only (Default 14'b11111100000000)
1
RX_DESCR_20_EN
1 = Enable 20 bit descrambler (pre-decoder) on transmit side(Default 1’b0)
0 = Disable 20 bit descrambler (pre-decoder) on transmit side
0
RX_DESCR_16_EN
1 = Enable 16 bit descrambler (post-decoder) on transmit side. Seed can be set
through 0x801C and 0x801D (Default 1’b0)
0 = Disable 16 bit descrambler (post-decoder) on transmit side
Access
RW
RW
RW
Table 6-54. VS_RX_DESCR_SEED_CONTROL_1
Register Address:0x801C SPACER Default: 0x0000
Bit(s) Name
Description
15:0
RX_DESCR_SEED[31:16]
[31:16] bits of 32 bit Rx descrambler seed. RX_DESCR_SEED[31:0] must be set to
a non-zero value for descrambler to work properly (Default 16’h0000).
Access
RW
Table 6-55. VS_RX_DESCR_SEED_CONTROL_0
Register Address:0x801D SPACER Default: 0x01FC
Bit(s) Name
Description
15:0
RX_DESCR_SEED[15:0]
[15:0] bits of 32 bit Rx descrambler seed. Bit 0 always set to 1’b0.
RX_DESCR_SEED[31:0] must be set to a non-zero value for descrambler to work
properly (Default 16’h01FC).
Access
RW
Table 6-56. VS_RX_DESCR_POLY_CONTROL_1
Register Address:0x801E SPACER Default: 0x0000
Bit(s) Name
Description
15:0
RX_DESCR_POLY[31:16]
[31:16] bits of 32 bit Rx descrambler polynomial (Default 16’h0000).
Access
RW
Table 6-57. VS_RX_DESCR_POLY_CONTROL_0
Register Address:0x801F SPACER Default: 0x00C0
Bit(s) Name
Description
15:0
RX_DESCR_POLY[15:0]
[15:0] bits of 32 bit Rx descrambler polynomial. Bit 0 always set to 1’b0. (Default
16’h00C0).
Access
RW
Copyright © 2013, Texas Instruments Incorporated
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