TLK10081 Datasheet, PDF (3/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
2 PHYSICAL CHARACTERISTICS
SLLSEE9 – NOVEMBER 2013
2.1 Block Diagram
A simplified block diagram of the TLK10081 device for 8:1 mode is shown in Figure 2-1 and Figure 2-2.
This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low speed
side and the other on the high speed side. The core logic block that lies between the two SERDES blocks
carries out all the logic functions including test pattern generation and verification.
The TLK10081 provides a management data input/output (MDIO) control interface as well as a JTAG
interface for device configuration, control, and monitoring. Detailed descriptions of the TLK10081 pin
functions are provided in Figure 2-1.
TLK10081 TX
Read
Controller
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
CH
SYNC
M
U
X
8b/10b
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
0
1
M
U
LN0
X _MARK
2
3
M
U 8b/10b
X
M
U
X
M
U SCR
X
M
U 8b/10b
X
M
U
X
M
U SCR
X
Figure 2-1. A Simplified Block Diagram of the TLK10081 (TX)
Copyright © 2013, Texas Instruments Incorporated
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PHYSICAL CHARACTERISTICS
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