TLK10081 Datasheet, PDF (6/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
Table 2-1. Pin Description - Signal Pins (continued)
TERMINAL
SIGNAL
BGA
DIRECTION
TYPE
SUPPLY
DESCRIPTION
LOSB
Channel B Receive Loss of Signal (LOS) Indicator.
LOSB=0: Signal detected.
LOSB=1: Loss of signal.
Loss of signal detection is based on the input signal level. When HSRXBP/N has a differential
input signal swing of ≤75 mVpp, LOSB will be asserted (if enabled). If the input signal is greater
Output
than 150 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is
LVCMOS
undefined.
K8
1.5V/1.8V
VDDO1
Other functions can be observed on LOSB real-time, configured via MDIO.
40Ω Driver
During device reset (RESET_N asserted low) this pin is driven low. During pin based power down
(PDTRXB_N asserted low), this pin is floating. During register based power down, this pin is
floating.
It is highly recommended that LOSB be brought to an easily accessible point on the application
board (header) in the event that debug is required.
RXCTRL_1
L8
Input
LVCMOS
1.5V/1.8V
VDDO1
Channel B Bit Interleave Lane Rotation Jog.
A toggle of this pin, either from high to low or from low to high, causes a lane rotation of the
HSRXBP/N source data.
GPO1
Output
H9
LVCMOS
1.5V/1.8V
VDDO1
Channel B General Purpose Output.
This pin should be left unconnected in the device application.
40Ω Driver
PDTRXB_N
J4
Input
LVCMOS
1.5V/1.8V
VDDO1
Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in power
down mode. When deasserted, Channel B operates normally. After deassertion, a software data
path reset should be issued through the MDIO interface.
REFERENCE CLOCKS AND CONTROL AND MONITORING SIGNALS
REFCLK0P/N
M10 / M11
Input
LVDS/LVPECL
DVDD
Reference Clock Input Zero. This differential input is a clock signal used as a reference to one or
both channels.The reference clock selection is done through MDIO or REFCLKA_SEL and
REFCLKB_SEL pins. This input signal must be AC coupled. If unused, REFCLK0P/N should be
pulled down to GND through a shared 100 ohm resistor.
REFCLK1P/N
K9 / K10
Input
LVDS/LVPECL
DVDD
Reference Clock Input One. This differential input is a clock signal used as a reference to one or
both channels. The reference clock selection is done through MDIO. This input signal must be AC
coupled. If unused, REFCLK1P/N should be pulled down to GND through a shared 100 ohm
resistor.
REFCLK_SEL
H10
Input
LVCMOS
1.5V/1.8V
VDDO0
Reference Clock Select. This input, when low, selects REFCLK0P/N as the clock reference to
Channel A/B SERDES. When high, REFCLK1P/N is selected as the clock reference to Channel
A/B SERDES. If software control is desired, this input signal should be tied low. Default reference
clock for Channel A/B is REFCLK0P/N.
CLKOUTAP/N
CLKOUTBP/N
C9/C10
A9/A10
Output
CML
DVDD
Channel A/B Output Clock. By default, this output is enabled and outputs the high speed side
Channel A recovered byte clock (high speed line rate divided by 20). Optionally it can be
configured to output the VCO clock divided by 2. Additional MDIO-selectable divide ratios of 1, 2,
4, 5, 8, 10, 16, 20, and 25 are available. See Figure 5-1.
These CML outputs must be AC coupled.
During device reset (RESET_N asserted low) these pins are driven differential zero.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), these pins are
floating.
During register based power down, these pins are floating.
PRBSEN
Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits
Input
are enabled on both transmit and receive data paths on high speed and low speed sides of both
B9
LVCMOS
1.5V/1.8V
VDDO0
channels.
This signal is logically OR’d with MDIO register bits A.13:12, and B.13:12.
PRBS 2³¹-1 is selected by default, and can be changed through MDIO.
PRBS_PASS
J9
Output
LVCMOS
/1.8V
VDDO1
40Ω Driver
Receive PRBS Error Free (Pass) Indicator.
When PRBS test is enabled (PRBSEN=1):
PRBS_PASS=1 indicates that PRBS pattern reception is error free.
PRBS_PASS=0 indicates that a PRBS error is detected. The channel, high speed or low speed
side, and lane (for low speed side) that this signal refers to is chosen through MDIO register bits
0.3:0.
During device reset (RESET_N asserted low) this pin is driven low.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating.
During register based power down, this pin is floating.
It is highly recommended that PRBS_PASS be brought to easily accessible point on the
application board (header), in the event that debug is required.
6
PHYSICAL CHARACTERISTICS
Submit Documentation Feedback
Product Folder Links: TLK10081
Copyright © 2013, Texas Instruments Incorporated