TLK10081 Datasheet, PDF (19/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
5 CLOCKING
SLLSEE9 – NOVEMBER 2013
5.1 Configuring PLL and Line Rates
The TLK10081 includes internal low-jitter high quality oscillators that are used as frequency multipliers for
the low speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers
are available for SERDES rate and PLL multiplier selection to match line rates and reference clock
(REFCLK0/1) frequencies for various applications. Some examples are detailed below on how to select
and configure.
The external differential reference clock has a large operating frequency range allowing support for many
different applications. The reference clock frequency must be within ± 200 PPM of the incoming serial data
rate (± 100 PPM of nominal data rate).
Table 5-1. Line Rate and Reference Clock Selection for the 1:1 Mode
LOW SPEED SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE
REFCLKP/N
(MHz)
1000-1250
10
Half
100-125
1000-1250
8
Half
125-156.25
1000-1250
8
Quarter
250-312.5
(1) High Speed Side SERDES runs at 2x effective data rate.
LINE RATE
(Mbps⁽¹⁾ )
1000-1250
1000-1250
1000-1250
HIGH SPEED SIDE
SERDES PLL
MULTIPLIER
RATE
20
Quarter
16
Quarter
8
Quarter
REFCLKP/N
(MHz)
100-125
125-156.25
250-312.5
For other line rates in 8:1 mode, valid reference clock frequencies can be selected with the help of the
information provided in Table 5-2 and Table 5-3 for the low speed side and high speed side SERDES. The
reference clock frequency has to be the same for the two SERDES and must be within the specified valid
ranges for different PLL multipliers.
Table 5-2. Line Rate and Reference Clock Frequency Ranges for the Low Speed Side SERDES
SERDES PLL
MULTIPLIER (MPY)
4
5
6
8
10
REFERENCE CLOCK (MHz)
MIN
MAX
250
425
200
425
166.667
416.667
125
312.5
122.88
250
HALF RATE (Gbps)
MIN
MAX ⁽¹⁾
1
1.25
1
1.25
1
1.25
1
1.25
1.2288
1.25
(1) Reference Clock is lower than Max Reference Clock RateScale: Half Rate = 1, Quarter Rate = 2
QUARTER RATE (Gbps)
MIN
MAX
0.5
0.85
0.5
1.0625
0.5
1.25
0.5
1.25
0.6144
1.25
Table 5-3. Line Rate and Reference Clock Frequency Ranges for the High Speed Side SERDES
SERDES PLL
MULTIPLIER (MPY)
4
5
6
8
10
12
15
16
20
REFERENCE CLOCK (MHz)
MIN
MAX
375
425
300
425
250
416.667
187.5
312.5
150
250
125
208.333
122.88
166.667
122.88
156.25
122.88
125
FULL RATE (Gbps)
MIN
MAX
6
6.8
6
8.5
6
10
6
10
6
10
6
10
7.3728
10
7.864
10
9.8304
10
(1) Reference Clock is higher than Min Reference Clock
RateScale: Full Rate = 0.25, Half Rate = 0.5, Quarter Rate = 1
HALF RATE (Gbps)
MIN
MAX
4 ⁽¹⁾
4 ⁽¹⁾
4 ⁽¹⁾
4 ⁽¹⁾
4 ⁽¹⁾
4 ⁽¹⁾
4 ⁽¹⁾
4.9152
4.25
5
5
5
5
5
5
5
QUARTER RATE (Gbps)
MIN
MAX
2 ⁽¹⁾
2 ⁽¹⁾
2 ⁽¹⁾
2 ⁽¹⁾
2 ⁽¹⁾
2 ⁽¹⁾
2 ⁽¹⁾
2.4576
2.125
2.5
2.5
2.5
2.5
2.5
2.5
2.5
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