TLK10081 Datasheet, PDF (35/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
Table 6-21. LS_TP_OVERLAY_CONTROL (continued)
Register Address:0x0A SPACER Default:0x0500
Bit(s) Name
Description
0
LS_LOS_OVERLAY
0 = LOSx pin does not reflect LS Serdes lane Loss of signal condition (Default 1’b0)
1 = Allows LS serdes lane Loss of signal condition to be reflected on LOSx pin
Access
RW
Table 6-22. HS_TP_CONTROL
Register Address:0x0B SPACER Default:0x0520
Bit(s)
Name
Description
15:14
RESERVED
For TI use only.
13
HS_TP_GEN_EN
0 = Normal operation (Default 1’b0)
1 = Activates test pattern generation selected by bits 11.10:8
12
HS_TP_VERIFY_EN
0 = Normal operation (Default 1’b0)
1 = Activates test pattern verification selected by bits 11.10:8
10:8
HS_TEST_PATT_SEL[2:0]
Test Pattern Selection. Refer Test pattern procedures section for more
information.
000 = High Frequency Test Pattern
001 = Low Frequency Test Pattern
010 = Mixed Frequency Test Pattern
011 = CRPAT Long
100 = CRPAT Short
101 = 2⁷ - 1 PRBS pattern (Default 3’b101)
110 = 2²³ - 1 PRBS pattern
111 = 2³¹ - 1 PRBS pattern
Errors can be checked by reading HS_ERROR_COUNT register.
7:6
RESERVED
For TI use only (Default 2’b00)
5:4
LS_PRBS_SEL[2:0]
Test Pattern Selection. Refer Test pattern procedures section for more
information.
00 = 2³¹ - 1 PRBS pattern
01 = Reserved.
10 = 2⁷ - 1 PRBS pattern (Default 2’b10)
11 = 2²³ - 1 PRBS pattern
3
DEEP_REMOTE_LPBK
0 = Normal functional mode (Default 1’b0)
1 = Enable deep remote loopback mode
2:0
RESERVED
For TI use only (Default 3’b000)
Access
RW
RW
RW
RW
RW
RW
RW
RW
Table 6-23. CLK_SEL_CONTROL
Register Address:0x0D SPACER Default:0x0000
Bit(s)
Name
Description
15:12
LS_TX_FIFO_RESET[7:4]
Reset control for LS lanes 7/6/5/4 FIFO on transmit path (Default 4’b0000)
[7] for Lane 7, [6] for Lane 6, [5] for Lane 5, [4] for Lane 4.
11:8
LS_TX_FIFO_RESET[3:0]
Reset control for LS lanes 3/2/1/0 FIFO on transmit path (Default 4’b0000)
[3] for Lane 3, [2] for Lane 2, [1] for Lane 1, [0] for Lane 0.
7:6
LANE7_CLK_SEL
00 = Selects LS lane 4 Tx Byteclk as clock for lane 7 (Default 2’b00)
01 = Selects LS lane 6 Tx Byteclk as clock for lane 7
1x = Selects LS lane 7 Tx Byteclk as clock for lane 7
5
LANE6_CLK_SEL
0 = Selects LS lane 4 Tx Byteclk as clock for lane 6 (Default 1’b0)
1 = Selects LS lane 6 Tx Byteclk as clock for lane 6
4
LANE5_CLK_SEL
0 = Selects LS lane 4 Tx Byteclk as clock for lane 5 (Default 1’b0)
1 = Selects LS lane 5 Tx Byteclk as clock for lane 5
3:2
LANE3_CLK_SEL
00 = Selects LS lane 0 Tx Byteclk as clock for lane 3 (Default 2’b00)
01 = Selects LS lane 2 Tx Byteclk as clock for lane 3
1x = Selects LS lane 3 Tx Byteclk as clock for lane 3
1
LANE2_CLK_SEL
0 = Selects LS lane 0 Tx Byteclk as clock for lane 2 (Default 1’b0)
1 = Selects LS lane 2 Tx Byteclk as clock for lane 2
0
LANE1_CLK_SEL
0 = Selects LS lane 0 Tx Byteclk as clock for lane 1 (Default 1’b0)
1 = Selects LS lane 1 Tx Byteclk as clock for lane 1
Access
RW/SC
RW/SC
RW
RW
RW
RW
RW
RW
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