TLK10081 Datasheet, PDF (23/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
www.ti.com
SLLSEE9 – NOVEMBER 2013
The following timing diagrams illustrate an example write transaction to Register 16’h8000 using indirect
addressing in Clause 22.
MDC
MDIO
0 1 0 1 PA[4:0]
5'h1E
1 0 16'h9000
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 6-3. CL22 – Indirect Address Method – Address Write
MDC
MDIO
0 1 0 1 PA[4:0]
5'h1F
10
DATA
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 6-4. CL22 - Indirect Address Method – Data Write
The following timing diagrams illustrate an example read transaction to read contents of Register 16’h8000
using indirect addressing in Clause 22.
MDC
MDIO
0 1 0 1 PA[4:0]
5'h1E
1 0 16'h9000
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 6-5. CL22 - Indirect Address Method – Address Write
MDC
MDIO
0 1 1 0 PA[4:0]
5'h1F
Z
0 D15 D0 ¹
> 32 "1's"
Preamble
Start
Read
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Note that the 1 in the Turn Around section is externally pulled up, and driven to Zero by TLK10081.
Figure 6-6. CL22 - Indirect Address Method – Data Read
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