TLK10081 Datasheet, PDF (31/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
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VALUE
0000
0001
0010
0011
0100
0101
0110
0111
Table 6-12. HSTX Pre-Cursor Transmit Tap Weights
5.7:4
TAP WEIGHT (%)
0
+2.5
+5.0
+7.5
+10.0
+12.5
+15.0
+17.5
VALUE
1000
1001
1010
1011
1100
1101
1110
1111
5.7:4
SLLSEE9 – NOVEMBER 2013
TAP WEIGHT (%)
0
–2.5
–5.0
–7.5
–10.0
–12.5
–15.0
–17.5
Table 6-13. LS_SERDES_CONTROL_1
Register Address:0x06 SPACER Default:0x8115
Bit(s)
Name
Description
15
GLOBAL_LN_WRITE Global lane write enable.
0 = Control settings are specific to lane addressed. Lane can be specified through
LS_LN_CFG_EN
1 = Control settings written to lane specific registers are applied to all lanes (Default
1’b1)
Lane specific registers are LS_SERDES_CONTROL_2 & LS_SERDES_CONTROL_3
& LS_TP_OVERLAY_CONTROL & LS_ALIGN_CODE_CONTROL &
LS_LOS_TXFIFO_CONTROL & LN_DATA_SRC_CONTROL & LS_CH_CONTROL_1
14:12
LS_LN_CFG_EN[2:0]
LS lane cfg control. Writes to lane specific control registers
LS_SERDES_CONTROL_2 & LS_SERDES_CONTROL_3 &
LS_TP_OVERLAY_CONTROL & LS_ALIGN_CODE_CONTROL &
LS_LOS_TXFIFO_CONTROL & LN_DATA_SRC_CONTROL & LS_CH_CONTROL_1
are applicable to lane selected (Applicable when GLOBAL_LN_WRITE is LOW). Selects
selected lane status to be reflected in LS_LN_ERROR_COUNTER &
LS_RXLOS_DET_ERR_COUNT & LS_STATUS_1
000 = Lane 0 access (Default 3’b000)
001 = Lane 1 access
010 = Lane 2 access
011 = Lane 3 access
100 = Lane 4 access
101 = Lane 5 access
110 = Lane 6 access
111 = Lane 7 access
11:10
RESERVED
For TI use only (Default 2’b00)
9:8
LS_LOOP_
LS Serdes PLL Loop Bandwidth settings
BANDWIDTH[1:0]
00 = Reserved
01 = Applicable when external JC_PLL is NOT used (Default 2’b01)
10 = Applicable when external JC_PLL is used
11 = Reserved
7:5
RESERVED
For TI use only (Default 3’b000)
4
LS_ENPLL
LS Serdes PLL enable control. LS Serdes PLL is automatically disabled when
PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.
0 = Disables PLL in LS serdes
1 = Enables PLL in LS serdes (Default 1’b1)
3:0
LS_MPY[3:0]
LS Serdes PLL multiplier setting (Default 4’b0101).
Refer to Table 6-14.
Access
RW
RW
RW
RW
RW
RW
RW
VALUE
0000
0001
0010
Table 6-14. LS PLL Multiplier Control
6.3:0
PLL MULTIPLIER FACTOR
4x
5x
6x
VALUE
1000
1001
1010
Copyright © 2013, Texas Instruments Incorporated
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6.3:0
PLL MULTIPLIER FACTOR
15x
20x
25x
PROGRAMMERS REFERENCE
31