TLK10081 Datasheet, PDF (36/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
Table 6-24. RESET_CONTROL
Register Address:0x0E SPACERDefault:0x0000
Bit(s)
Name
Description
15:12
LS_RX_FIFO_RESET[7:4]
Reset control for LS lanes 4-7 FIFO on receive path (Default 4’b0000)
[7] for Lane 7, [6] for Lane 6, [5] for Lane 5, [4] for Lane 4.
11:8
LS_RX_FIFO_RESET[3:0] Reset control for LS lanes 0-3 FIFO on receive path (Default 4’b0000)
[3] for Lane 3, [2] for Lane 2, [1] for Lane 1, [0] for Lane 0.
7
HS_TX_FIFO_RESET
Reset control for HS FIFO on transmit path (Default 1’b0)
6
HS_RX1_FIFO_RESET
Reset control for HS RX1 FIFO (Default 1’b0)
5
HS_RX0_FIFO_RESET
Reset control for HS RX0 FIFO (Default 1’b0)
4
LT_RESTART_TRAINING 1 = Restart link/auto train
0 = Normal operation (Default 1’b0)
3
DATAPATH_RESET
Channel datapath reset control. Required once the desired functional mode is
configured.
0 = Normal operation. (Default 1’b0)
1 = Resets channel logic excluding MDIO registers. (Resets both Tx and Rx
datapath)
2:0
RESERVED
For TI use only (Default 3’b000)
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
Access
RW
SC ⁽¹⁾
Table 6-25. CHANNEL_STATUS_1
Register Address:0x0F SPACER Default:0x0000
Bit(s) Name
Description
15
HS_TP_STATUS
Test Pattern status for HS High/Low/Mixed/CRPAT test patterns.
1 = Alignment has achieved and correct pattern has been received. Any bit errors
are reflected in HS_ERROR_COUNTER register (0x10)
0 = Alignment has not been determined
14
LS_TRAINING_FAIL
1 = Training failure has been detected
0 = Training failure has not been detected
13
HS_LOS
Loss of Signal Indicator.
When high, indicates that a loss of signal condition is detected on HS serial
receive inputs
12
HS_AZ_DONE
Auto zero complete indicator.
When high, indicates auto zero calibration is complete
11
HS_AGC_LOCKED
Adaptive gain control loop lock indicator.
When high, indicates AGC loop is in locked state
10
HS_CHANNEL_SYNC
Channel synchronization status indicator.
When high, indicates channel synchronization has achieved
9
RESERVED
For TI use only
8
HS_DECODE_INVALID
Valid when decoder is enabled and during CRPAT test pattern verification. When
high, indicates decoder received an invalid code word, or a 8b/10b disparity error.
In functional mode, number of DECODE_INVALID errors are reflected in
HS_ERROR_COUNTER register (0x10)
7
HS_TX0_FIFO_UNDERFLOW When high, indicates overflow has occurred in the transmit datapath lane (CTC)
FIFO.
6
HS_TX0_FIFO_OVERFLOW
When high, indicates overflow has occurred in the transmit datapath lane (CTC)
FIFO.
5
RESERVED
For TI use only
4
BIT_LM_DONE
Applicable only when HS_RX_BIT_INTERLEAVE is set to 1. When high,
indicates lane marker detection state machine searched all possible LS lanes,
and found valid marker pattern
3
LT_FRAME_LOCK
1 = Training frame delineation detected
0 = Training frame delineation not detected
2
LT_RX_STATUS
1 = Receiver trained and ready to receive data
0 = Receiver training in progress
1
LS_PLL_LOCK
LS Serdes PLL lock indicator
When high, indicates LS Serdes PLL achieved lock to the selected incoming
REFCLK0/1_P/N
Access
RO
RO/LH
RO/LH
RO/LL
RO/LL
RO/LL
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO
RO
RO/LL
36
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