TLK10081 Datasheet, PDF (38/62 Pages) Texas Instruments – 10Gbps 1-8 CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR

TLK10081
SLLSEE9 – NOVEMBER 2013
www.ti.com
Table 6-28. LS_STATUS_1⁽¹⁾
Register Address:0x13 SPACERDefault:0x0000
Bit(s)
Name
Description
15
LS_TP_STATUS
Test Pattern status for LS High/Low/Mixed/CRPAT test patterns.
1 = Alignment has achieved and correct pattern has been received. Any bit errors
are reflected in LS_LN_ERROR_COUNTER register
0 = Alignment has not been determined
14
LS_RXLOS_DETECT
When high, indicates LOS state machine successfully detected valid LOS pattern
for the selected lane. This bit is raw status of LS_ RXLOS_DETECT_LH
13:12
RESERVED
For TI use only.
11
LS_INVALID_DECODE
LS Invalid decode error for selected lane. Error count for each lane can also be
monitored through respective LS_LN_ERROR_COUNTER registers
10
LS_LOS
Loss of Signal Indicator. When high, indicates that a loss of signal condition is
detected on LS serial receive inputs for selected lane.
9
LS_RXLOS_DETECT_LH When high, indicates LOS state machine successfully detected valid LOS pattern
for the selected lane.
8
LS_CH_SYNC_STATUS
LS Channel sync status for selected lane.
7:4
RESERVED
For TI use only.
3
LS_TX_FIFO_UNDERFLOW When high, indicates underflow has occurred in the transmit datapath lane (CTC)
FIFO.
2
LS_TX_FIFO_OVERFLOW When high, indicates overflow has occurred in the transmit datapath lane (CTC)
FIFO.
1
LS_RX_FIFO_UNDERFLOW When high, indicates underflow has occurred in the receive datapath lane (CTC)
FIFO.
0
LS_RX_FIFO_OVERFLOW When high, indicates overflow has occurred in the receive datapath lane (CTC)
FIFO.
(1) This is per lane status register. Lane can be selected through LS_LN_CFG[14:12] (Register 0x06)
Access
RO
RO
RO
RO/LH
RO/LH
RO/LH
RO/LL
RO
RO/LH
RO/LH
RO/LH
RO/LH
Table 6-29. HS_STATUS_1
Register Address:0x14 SPACER Default:0x0000
Bit(s) Name
Description
15
RX3_LANE_ALIGN
RX3 lane align status on receive path
14
RX2_LANE_ALIGN
RX2 lane align status on receive path
13
TX3_LANE_ALIGN
TX3 lane align status on transmit path
12
TX2_LANE_ALIGN
TX2 lane align status on transmit path
11
RX1_LANE_ALIGN
RX1 lane align status on receive path
10
RX0_LANE_ALIGN
RX0 lane align status on receive path
9
TX1_LANE_ALIGN
TX1 lane align status on transmit path
8
TX0_LANE_ALIGN
TX0 lane align status on transmit path
7:4
RESERVED
For TI use only.
3
HS_RX1_FIFO_UNDERFLOW When high, indicates underflow has occurred in the receive datapath lane FIFO
when alternate macro HS Rx data is selected.
2
HS_RX1_FIFO_OVERFLOW When high, indicates overflow has occurred in the receive datapath lane FIFO
when alternate macro HS Rx data is selected.
1
HS_RX0_FIFO_UNDERFLOW When high, indicates underflow has occurred in the receive datapath lane FIFO.
0
HS_RX0_FIFO_OVERFLOW When high, indicates overflow has occurred in the receive datapath lane FIFO.
Access
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO
RO/LH
RO/LH
RO/LH
RO/LH
38
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