K522H1HACF-B050 Datasheet, PDF (73/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
13. WRITE INTERRUPTED BY A READ & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the inter-
rupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must
be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that
are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be
issued at the next clock edge of that of write command.
0
1
2
3
CK
CK
4
5
6
Command NOP
WRITE
NOP
tDQSS(max)
DQS
tDQSS(max)
Hi-Z
tWPRES
NOP
NOP
READ
tCDLR
NOP
DQs
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
DM
tDQSS(min)
DQS
DQs
Hi-Z
tDQSS(min)
tCDLR
tWPRES
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
7
8
9
NOP
NOP
NOP
NOP
Dout0 Dout1 Dout2 Dout3 Dout4
Dout0 Dout1 Dout2 Dout3 Dout4
DM
NOTE :
1) Burst Length=8, CAS Latency=3 .
Figure 9. Write interrupted by a Read and DM timing
The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
1. For Read commands interrupting a burst Write, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay
is 1 clock cycle is disallowed.
2. For Read commands interrupting a burst Write, the DM pin must be used to mask the input data words which immediately precede the interrupting
Read operation and the input data word which immediately follows the interrupting Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow
the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the Mobile DDR SDRAM.
5. Refer to Burst write operation.
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