K522H1HACF-B050 Datasheet, PDF(11/94 Page) Samsung semiconductor

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K522H1HACF-B050 Datasheet, PDF (11/94 Pages) Samsung semiconductor – MCP Specification

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K522H1HACF-B050

datasheet

Rev. 1.0

MCP Memory

Figure 1. Functional Block Diagram(x8)

VCC

VSS

A12 - A29*

X-Buffers

Latches

& Decoders

2,048M + 64M Bit for 2Gb

4,096M + 128M Bit for 4Gb DDP

NAND Flash

ARRAY

A0 - A11

Y-Buffers

Latches

& Decoders

Data Register & S/A

Y-Gating

Command

Control Logic

& High Voltage

Generator

CLE ALE WP

I/O Buffers & Latches

VCC

VSS

Global Buffers

Output

Driver

I/0 0

I/0 7

Figure 2. Array Organization(x8)

1 Block = 64 Pages

(128K + 4K) Byte

2,048 blocks for 2Gb

4,096 blocks for 4Gb DDP

2K Bytes

64 Bytes

1 Page = (2K + 64)Bytes

1 Block = (2K + 64)Byte x 64 Pages

= (128K + 4K) Bytes

1 Device = (2K+64)B x 64Pages x 2,048 Blocks

= 2,112 Mbits for 2Gb

8 bit 1 Device = (2K+64)B x 64Pages x 4,096 Blocks

= 4,224 Mbits for 4Gb DDP

Page Register

2K Bytes

I/O 0 ~ I/O 7

64 Bytes

I/O

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

I/O 0

A12

A20

A28

I/O 1

A13

A21

*A29

I/O 2

A10

A14

A22

[Table 1] Array address : (x8)

I/O 3

I/O 4

I/O 5

A11

A15

A16

A17

A23

A24

A25

NOTE :

Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

* A29 is Row address for 4G DDP.

In case of 2G Mono, A29 must be set to "Low"

I/O 6

A18

A26

I/O 7

A19

A27

Address

Column Address

Row Address

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