K522H1HACF-B050 Datasheet, PDF (39/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
4.4 BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only
Block address is valid while page address is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing
process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is
completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
I/Ox
60h
Address Input(3Cycle)
D0h
Row Add 1,2,3
"0"
70h
I/O0
Pass
"1"
Fail
4.5 READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase
operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/
O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple mem-
ory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status
Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read
during a random read cycle, the read command(00h) should be given before starting read cycles.
I/O
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Page Program
Pass/Fail
Not use
Not use
Not Use
Not Use
Not Use
Ready/Busy
Write Protect
[Table 4] Status Register Definition for 70h Command
Block Erase
Read
Pass/Fail
Not Use
Pass : "0"
Not use
Not use
Don’t -cared
Not use
Not use
Don’t -cared
Not Use
Not use
Don’t -cared
Not Use
Not Use
Don’t -cared
Not Use
Not Use
Don’t -cared
Ready/Busy
Ready/Busy
Busy : "0"
Write Protect
Write Protect
Protected : "0"
Definition
Fail : "1"
Ready : "1"
Not Protected : "1"
NOTE :
1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
4.6 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles
sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID
mode until further commands are issued to it. Figure 14 shows the operation sequence.
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