K522H1HACF-B050 Datasheet, PDF(12/94 Page) Samsung semiconductor

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K522H1HACF-B050 Datasheet, PDF (12/94 Pages) Samsung semiconductor – MCP Specification

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K522H1HACF-B050

datasheet

Rev. 1.0

MCP Memory

Figure 3. unctional Block Diagram(x16)

VCC

VSS

A11 - A28*

X-Buffers

Latches

& Decoders

2,048M + 64M Bit for 2Gb

4,096M + 128M Bit for 4Gb DDP

NAND Flash

ARRAY

A0 - A10

Y-Buffers

Latches

& Decoders

Data Register & S/A

Y-Gating

Command

Control Logic

& High Voltage

Generator

CLE ALE WP

I/O Buffers & Latches

VCC

VSS

Global Buffers

Output

Driver

I/0 0

I/0 15

Figure 4. Figure 2-2. Array Organization(x16)

1 Block = 64 Pages

(64K + 2K)Word

2,048 blocks for 2Gb

4,096 blocks for 4Gb DDP

1K Words

32 Words

1 Page = (1K + 32)Word

1 Block = (1K + 32)Word x 64 Pages

= (64K + 2K)Words

1 Device = (1K + 32)Word x 64Pages x 2,048 Blocks

= 2,112 Mbits for 2Gb

16 bit 1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks

= 4,224 Mbits for 4Gb DDP

Page Register

1K Words

I/O 0 ~ I/O 15

32 Words

[Table 2] Array address : (x16)

I/O

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

1st Cycle

2nd Cycle

A10

3rd Cycle

A11

A12

A13

A14

A15

A16

A17

4th Cycle

A19

A20

A21

A22

A23

A24

A25

5th Cycle

A27

*A28

NOTE :

Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

* A28 is Row address for 4G DDP.

In case of 2G Mono, A28 must be set to "Low"

I/O 7

A18

A26

I/O 8~I/O 15

Address

Column Address

Row Address

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