K522H1HACF-B050 Datasheet, PDF (68/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
7. BURST WRITE OPERATION
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock (CK). The address inputs
determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be
applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CK) that the write com-
mand is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed.
When the burst has been finished, any additional data supplied to the DQ pins will be ignored.
0
1
2
3
4
5
6
CK
CK
Command ^NOP
WRITEA
NOP
WRITEB
NOP
NOP
NOP
tDQSS(max)
DQS
DQs
tDQSS(max)
Hi-Z
tWPRES^tWPREH
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
tDQSS(min)
DQS
DQs
tDQSS(min)
Hi-Z
tWPRES tWPREH
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
tDS tDH
Figure 3. Burst write operation timing
NOTE :
1) Burst Length=4.
2) The specific requirement is that DQS be valid (High or Low) on or before this CK edge.
The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
7
NOP
tWR
tWR
8
NOP
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