K522H1HACF-B050 Datasheet, PDF (47/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
3.0 MODE REGISTER DEFINITION
3.1 Mode Register Set (MRS)
The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length,
test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The mode register is written by asserting low on
CS, RAS, CAS and WE (The Mobile DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of
address pins A0 ~ A13 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are
required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed
afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks
are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3,
Cas latency (read latency from column address) uses A4 ~ A6, A7 ~ A13 is used for test mode. BA0 and BA1 must be set to low for proper MRS opera-
tion.
BA1 BA0
A13 ~ A10/AP
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
0
0
RFU¹⁾
0
0
0
CAS Latency
BT
Burst Length
Mode Register
A3
Burst Type
0
Sequential
1
Interleave
A6 A5 A4 CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Figure 2. Mode Register Set
NOTE :
1) RFU (Reserved for future use) should stay "0" during MRS cycle.
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Burst Type
Reserved
2
4
8
16
Reserved
Reserved
Reserved
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