K522H1HACF-B050 Datasheet, PDF (49/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
3.2 Extended Mode Register Set (EMRS)
The extended mode register is designed to support for the desired operating modes of DDR SDRAM. The extended mode register is written by asserting
low on CS, RAS, CAS, WE and high on BA1, low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing
into the extended mode register). The state of address pins A0 ~ A13 in the same cycle as CS, RAS, CAS and WE going low is written in the extended
mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished
and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But
this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A7 are used for driver
strength control. "High" on BA1 and "Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6,A7, BA1, BA0 must be set to
low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0
A13 ~ A10/AP
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
1
0
RFU¹⁾
0
0
DS
RFU¹⁾
PASR
Mode Register
DS
A7 A6 A5 Driver Strength
000
Full
001
1/2
010
1/4
011
1/8
100
3/4
101
3/8
110
5/8
111
7/8
PASR
A2 A1 A0 Refreshed Area
000
Full Array
001
1/2 Array
010
1/4 Array
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved
Figure 3. Extended Mode Register Set
NOTE :
1) RFU (Reserved for future use) should stay "0" during EMRS cycle.
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