K522H1HACF-B050 Datasheet, PDF (70/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
10. READ INTERRUPTED BY A PRECHARGE
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. The
latency from a precharge command to invalid output is equivalent to the CAS latency.
CK
CK
Command
0
1
1tCK
READ
Precharge
DQS
Hi-Z
DQs
Hi-Z
NOTE :
1) Burst Length=8, CAS Latency=3 .
2
3
4
5
6
7
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
tRPRE
tAC
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
Figure 6. Read interrupted by a precharge timing
8
NOP
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is
completed. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate
command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a burst Read, the Precharge command may be given on the rising clock edge which
is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after
tRP (Row Precharge time).
2. When a Precharge command interrupts a burst Read operation, the Precharge command given on a rising clock edge terminates the burst with the last
valid data word presented on DQ pins at CL-1(CL=CAS Latency) clock cycles after the command has been issued. Once the last data word has been
output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after tRP.
3. For a Read with Autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP from rising clock that comes
CL(CL=CAS Latency) clock cycles before the end of the Read burst. During Read with autoprecharge, the initiation of the internal precharge occurs at the
same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in
1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command
and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer
number of clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock
edge).In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This
includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same
timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
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