K522H1HACF-B050 Datasheet, PDF (4/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
2. GENERAL DESCRIPTION
The K522H1HACF is a Multi Chip Package Memory which combines 2G bit NAND Flash and 1G bit Mobile DDR synchronous Dynamic RAM.
NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250μs on the
(2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 42ns
cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates
all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive sys-
tems can take advantage of the device′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time map-
ping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
In 1Gbit Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system appli-
cations.
The K522H1HACF is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This
device is available in 153-ball FBGA Type.
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