K522H1HACF-B050 Datasheet, PDF (52/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
6.0 DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, T_C = -25 to 85°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
IDD0
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address
inputs are SWITCHING; data bus inputs are STABLE
Precharge Standby Current
in power-down mode
IDD2P
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2PS ^{all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge Standby Current
in non power-down mode
IDD2N
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active Standby Current
in power-down mode
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active Standby Current
in non power-down mode
(One Bank Active)
IDD3N
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3NS
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Operating Current
(Burst Mode)
IDD4R
IDD4W
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I _OUT =0 mA
address inputs are SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; tCK = tCKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
Refresh Current
IDD5
tRC ≥ tRFC; tCK = tCKmin; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
TCSR Range
Self Refresh Current
IDD6
CKE is LOW; t CK = t CKmin;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Full Array
1/2 Array
85°C
45°C
85°C
45°C
1/4 Array
85°C
45°C
NOTE :
1) IDD5 is measured in the below test condition.
Density 128Mb 256Mb 512Mb
1Gb
2Gb
Unit
t_RFC
80
80
110
140
140
ns
DDR400
60
0.5
0.5
8
4
5
4
12
10
70
50
70
Values
900
200
800
150
700
120
Unit Note
mA
mA
mA
mA
mA
mA
mA 1
uA
uA
5
uA
2) IDD specifications are tested after the device is properly initialized.
3) Input slew rate is 1V/ns.
4) Definitions for IDD: LOW is defined as V_IN ≤ 0.1 * VDDQ;
HIGH is defined as V_IN ≥ 0.9 * VDDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
5) IDD6 85°C is guaranteed, IDD6 45°C is typical value.
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