K522H1HACF-B050 Datasheet, PDF (69/94 Pages) Samsung semiconductor – MCP Specification

K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
8. READ INTERRUPTED BY A READ
A Burst Read can be interrupted by new Read command of any bank before completion of the burst. When the previous burst is interrupted, the new
address with the full burst length override the remaining address. The data from the first Read command continues to appear on the outputs until the CAS
latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read to Read interval is
minimum 1 Clock.
CK
CK
Command
DQS
DQs
0
1
tCCD(min)
READ
READ
Hi-Z
Hi-Z
2
3
4
5
6
NOP
NOP
NOP
NOP
NOP
tDQSCK
tRPRE
tRPST
Preamble
Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3
NOTE :
1) Burst Length=4, CAS Latency=3
Figure 4. Read interrupted by a read timing
7
NOP
8
NOP
9. READ INTERRUPTED BY A WRITE & BURST STOP
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQs (Output
drivers) in a high impedance state.
0
1
2
3
4
5
6
7
8
CK
CK
Command
READ
Burst Stop
DQS
Hi-Z
DQs
Hi-Z
NOP
tDQSCK
tRPRE
NOP
NOP
tRPST
tAC
Dout 0 Dout 1
WRITE
NOP
tDQSS
tWPREH
NOP
NOP
tWPRES
tWPST
Din 0 Din 1 Din 2 Din 3
NOTE :
1) Burst Length=4, CAS Latency=3 .
tWPRE
Figure 5. Read interrupted by a write and burst stop timing
The following functionality establishes how a Write command may interrupt a burst Read.
1. For Write commands interrupting a burst Read, a Burst Terminate command is required to stop the burst read and tri-state the DQ bus prior to valid
input write data. Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the Write command.
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
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