M16C6N4 Datasheet, PDF (99/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
10. Interrupt
Interrupt Control Register ⁽¹⁾
Symbol
Address
After Reset
b7 b6 b5 b4 b3 b2 b1 b0
0
INT3IC ⁽²⁾
C1RECIC/INT5IC ^{(2) (6)}
C1TRMIC/S3IC/INT4IC ^{(2) (7)}
INT0IC to INT2IC
0044h
0048h
0049h
005Dh to 005Fh
XX00X000b
XX00X000b
XX00X000b
XX00X000b
Bit Symbol
Bit Name
Function
RW
ILVL0
ILVL1
ILVL2
IR
Interrupt Priority Level
Select Bit
Interrupt Request Bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled) ^RW
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
RW
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
RW ⁽³⁾
POL
Polarity Select Bit
0 : Selects falling edge ^{(4) (5)}
1 : Selects rising edge
RW
-
(b5)
Reserved Bit
Set to "0"
RW
-
(b7-b6)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
NOTES:
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to 23.5 Interrupt.
2. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the
ILVL2 to ILVL0 bits in the INT5IC to INT3IC registers to "000b" (interrupt disabled).
3. This bit can only be reset by writing "0" (Do not write "1").
4. If the IFSR10 to IFSR15 bits in the IFSR1 register are "1" (both edges), set the POL bit in the INT0IC to INT5IC
register to "0" (falling edge).
5. Set the POL bit in the S3IC register to "0" (falling edge) when the IFSR00 bit in the IFSR0 register = 1 and the
IFSR16 bit in the IFSR1 register = 0 (SI/O3 selected).
6. Use the IFSR17 bit in the IFSR1 register to select.
7. Use the IFSR16 bit in the IFSR1 register and the IFSR00 bit in the IFSR0 register to select.
Figure 10.4 Interrupt Control Registers (2)
Rev.2.30 Oct 24, 2005 page 81 of 376
REJ09B0009-0230