M16C6N4 Datasheet, PDF (208/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
15. Serial Interface
Table 15.19 SI/O3 Specifications
Item
Specification
Transfer Data Format Transfer data length: 8 bits
Transfer clock
• SM36 bit in S3C register = 1 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n = Setting value of S3BRG register 00h to FFh
• SM36 bit = 0 (external clock) : Input from CLK3 pin ⁽¹⁾
Transmission/Reception Before transmission/reception can start, the following requirements must be met
Start Condition
Write transmit data to the S3TRR register ^{(2) (3)}
Interrupt Request
Generation Timing
• When SM34 bit in S3C register = 0
The rising edge of the last transfer clock pulse ⁽⁴⁾
CLK3 Pin Function
SOUT3 Pin Function
SIN3 Pin Function
• When SM34 bit = 1
The falling edge of the last transfer clock pulse ⁽⁴⁾
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
Select Function
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning
with bit 7 can be selected
• Function for setting an SOUT3 initial value set function
When the SM36 bit in the S3C register = 0 (external clock), the SOUT3 pin
output level while not transmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling
edge of transfer clock can be selected.
NOTES:
1. To set the SM36 bit in the S3C register to “0” (external clock), follow the procedure described below.
• If the SM34 bit in the S3C register = 0, write transmit data to the S3TRR register while input on the
CLK3 pin is high. The same applies when rewriting the SM37 bit in the S3C register.
• If the SM34 bit = 1, write transmit data to the S3TRR register while input on the CLK3 pin is low. The
same applies when rewriting the SM37 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/O3 circuit, stop
the transfer clock after supplying eight pulses. If the SM36 bit = 1 (internal clock), the transfer clock
automatically stops.
2. Unlike UART0 to UART2, SI/O3 is not separated between the transfer register and buffer. Therefore,
do not write the next transmit data to the S3TRR register during transmission.
3. When the SM36 bit = 1 (internal clock), SOUT3 retains the last data for a 1/2 transfer clock period after
completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the S3TRR register during this period, SOUT3 immediately goes to a high-impedance state,
with the data hold time thereby reduced.
4. When the SM36 bit = 1 (internal clock), the transfer clock stops in the high state if the SM34 bit = 0, or
stops in the low state if the SM34 bit = 1.
Rev.2.30 Oct 24, 2005 page 190 of 376
REJ09B0009-0230