M16C6N4 Datasheet, PDF (377/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
23. Usage Precaution
23.9 A/D Converter
Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before
a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF
connected), start A/D conversion after passing 1 µs or longer.
To prevent noise-induced device malfunction or latch-up, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0_i, and AN2_i) each and
the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 23.2 shows an
example connection of each pin.
Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the
__________
ADTRG pin is set to “0” (input mode).
When using key input interrupt, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
The φAD frequency must be 10 MHz or less. Without sample and hold, limit the φAD frequency to 250 kHz
or more. With the sample and hold, limit the φAD frequency to 1 MHz or more.
When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Microcomputer
VCC
AVCC
C4
VREF
C1
C2
VSS
AVSS
C3
ANi
ANi: ANi, AN0_i, and AN2_i (i =0 to 7)
NOTES:
1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference).
2. Use thick and shortest possible wiring to connect capacitors.
Figure 23.2 Use of Capacitors to Reduce Noise
Rev.2.30 Oct 24, 2005 page 359 of 376
REJ09B0009-0230