M16C6N4 Datasheet, PDF (74/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
8. Clock Generating Circuit
Peripheral Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0 0 00 0 0
Symbol
PCLKR
Address
025Eh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
Timers A, B, and A/D Clock
0 : Divide-by-2 of fAD, f2
PCLK0
Select Bit
1 : fAD, f1
(Clock source for the timers A, B,
RW
the dead time timer and A/D)
SI/O Clock Select Bit
0 : f2SIO
PCLK1 (Clock source for UART0 to UART2, _{1 : f1SIO}
RW
SI/O3)
-
(b7-b2)
Reserved Bit
Set to "0"
RW
NOTE:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
Figure 8.5 PCLKR Register
CAN0/1 Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CCLKR
Address
025Fh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
b2 b1 b0
CCLK0
0 0 0 No division
RW
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
CCLK1 CAN0 Clock Select Bits ^{(2) 0 1 1 : Divide-by-8}
RW
1 0 0: Divide-by-16
101:
CCLK2
1 1 0 : Do not set a value
RW
111:
CCLK3
CAN0 CPU Interface
Sleep Bit ⁽³⁾
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
RW
b6 b5 b4
CCLK4
0 0 0 No division
RW
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
CCLK5 CAN1 Clock Select Bits ^{(2) 0 1 1 : Divide-by-8}
RW
1 0 0 : Divide-by-16
101:
CCLK6
1 1 0 : Do not set a value
RW
111:
CCLK7
CAN1 CPU Interface
Sleep Bit ⁽³⁾
0: CAN1 CPU interface operating
1: CAN1 CPU interface in sleep
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (Write enabled).
2. Set only when the Reset bit in the CiCTLR register (i = 0, 1) = 1 (Reset/Initialization mode).
3. Before setting this bit to "1", set the Sleep bit in the CiCTLR to "1" (Sleep mode enabled).
Figure 8.6 CCLKR Register
Rev.2.30 Oct 24, 2005 page 56 of 376
REJ09B0009-0230