M16C6N4 Datasheet, PDF (98/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
10. Interrupt
10.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to
enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the
each interrupt control register.
Figures 10.3 and 10.4 show the interrupt control registers.
Interrupt Control Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C01WKIC ⁽⁵⁾
C0RECIC
C0TRMIC
TB5IC
TB4IC/U1BCNIC ⁽²⁾
TB3IC/U0BCNIC ⁽³⁾
U2BCNIC
DM0IC, DM1IC
C01ERRIC ⁽⁶⁾
ADIC/KUPIC ⁽⁷⁾
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Address
0041h
0042h
0043h
0045h
0046h
0047h
004Ah
004Bh, 004Ch
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Bit Symbol
Bit Name
Function
RW
ILVL0
ILVL1
ILVL2
Interrupt Priority Level
Select Bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled) ^RW
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
RW
1 1 1 : Level 7
0 : Interrupt not requested
IR
Interrupt Request Bit
1 : Interrupt requested
RW ⁽⁴⁾
-
(b7-b4)
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
NOTES:
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to 23.5 Interrupt.
2. Use the IFSR07 bit in the IFSR0 register to select.
3. Use the IFSR06 bit in the IFSR0 register to select.
4. This bit can only be reset by writing "0" (Do not write "1").
5. When the IFSR02 bit in the IFSR0 register = 0 (CAN0/1 wake-up or error), CAN0/1 wake-up is selected.
When the IFSR02 bit = 1 (CAN0 wake-up/error or CAN1 wake-up/error), CAN0 wake-up/error is selected.
6. When the IFSR02 bit = 0, CAN0/1 error is selected. When the IFSR02 bit = 1, CAN1 wake-up/error is selected.
7. Use the IFSR01 bit in the IFSR0 register to select.
Figure 10.3 Interrupt Control Registers (1)
Rev.2.30 Oct 24, 2005 page 80 of 376
REJ09B0009-0230