M16C6N4 Datasheet, PDF (133/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
13. Timers
Timer Ai Mode Register (i = 2 to 4)
(When using two-phase pulse signal processing)
b6 b5 b4 b3 b2 b1 b0
0 1 0 00 1
Symbol
TA2MR to TA4MR
Address
0398h to 039Ah
After Reset
00h
Bit Symbol
Bit Name
Function
RW
TMOD0
TMOD1
b1 b0
Operation Mode Select Bit _{0 1 : Event counter mode}
RW
RW
MR0
RW
To use two-phase pulse signal processing, set this bit to "0".
MR1
RW
MR2
To use two-phase pulse signal processing, set this bit to "1".
RW
MR3
To use two-phase pulse signal processing, set this bit to "0".
RW
TCK0
Count Operation Type
Select Bit
0 : Reload type
1 : Free-run type
RW
TCK1
Two-Phase Pulse Signal
Processing Operation
Select Bit ^{(1) (2)}
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
NOTES:
1. The TCK1 bit is valid for the TA3MR register. No matter how this bit is set, timers A2 and A4 always operate in normal
processing mode and x4 processing mode, respectively.
2. If two-phase pulse signal processing is desired, following register settings are required:
Set the TAiP bit in the UDF register to "1" (two-phase pulse signal processing function enabled).
Set the TAiTGH and TAiTGL bits in the TRGSR register to "00b" (TAiIN pin input).
Set the port direction bits for TAiIN and TAiOUT to "0" (input mode).
Figure 13.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
Rev.2.30 Oct 24, 2005 page 115 of 376
REJ09B0009-0230