M16C6N4 Datasheet, PDF(54/406 Page) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C6N4 Datasheet, PDF (54/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6N4)

6. Processor Mode

Processor Mode Register 1 (1)

b7 b6 b5 b4 b3 b2 b1 b0

00 0

Symbol

PM1

Address

0005h

After reset

00001000b

Bit symbol

PM10

Bit name

CS2 Area Switch Bit

(Data Block Enable Bit) (2)

Function

RW

0 : 08000h to 26FFFh (Block A disable)

1 : 10000h to 26FFFh (Block A enable)

RW

PM11

Port P3_7 to P3_4 Function 0 : Address output

Select Bit (3)

1 : Port function

RW

PM12

Watchdog Timer Function 0 : Watchdog timer interrupt

Select Bit

1 : Watchdog timer reset (4)

RW

PM13

Internal Reserved Area

Expansion Bit (5)

Internal ROM area is:

0 : 192 Kbytes or smaller

1 : Expanded over 192 Kbytes

RW

-

(b6-b4)

Reserved Bit

Set to "0"

RW

PM17

Wait Bit (6)

0 : No wait state

1 : With wait state (1 wait)

RW

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).

2. For the mask ROM version, this bit must be set to "0".

For the flash memory version, the PM10 bit also controls block A by enabling or disabling it. When the PM10

bit is set to "1", 0F000h to 0FFFFh (block A) can be used as internal ROM area.

In addition, the PM10 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite

mode).

3. Effective when the PM01 to PM00 bits are set to "01b" (memory expansion mode) or "11b" (microprocessor mode).

4. The PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.)

5. Be sure to set this bit to "0" except for products with internal ROM area over 192 Kbytes.

The PM13 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite mode).

6. When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM

or internal ROM.

When the PM17 bit is set to "1" and accesses an external area, set the CSiW bit (i = 0 to 3) in the CSR register

to "0" (with wait state).

Figure 6.2 PM1 Register

Rev.2.30 Oct 24, 2005 page 36 of 376

REJ09B0009-0230

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