M16C6N4 Datasheet, PDF (209/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
15.2.1 SI/O3 Operation Timing
Figure 15.38 shows the SI/O3 operation timing.
15. Serial Interface
"H"
SI/O3 internal clock _"L"
"H"
CLK3 output _"L"
Signal written to the "H"
S3TRR register "L"
SOUT3 output ^"H"
"L"
SIN3 input ^"H"
"L"
1.5 cycle (max.) ⁽¹⁾
D0
D1
D2
D3
D4
D5
D6
(NOTE 2)
D7
IR bit in S3IC register ^"1"
"0"
* This diagram applies to the case where the bits in the S3C register are set as follows:
SM32 = 0 (SOUT3 output)
SM33 = 1 (SOUT3 output, CLK3 function)
SM34 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
NOTES:
1. If the SM36 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
S3TRR register.
2. When the SM36 bit = 1 (internal clock), the SOUT3 pin is placed in the high-impedance state after the transfer finishes.
Figure 15.38 SI/O3 Operation Timing
15.2.2 CLK Polarity Selection
The SM34 bit in the S3C register allows selection of the polarity of the transfer clock.
Figure 15.39 shows the polarity of the transfer clock.
(1) When SM34 bit in S3C register = 0
CLK3
(NOTE 1)
SOUT3
D0 D1 D2 D3 D4 D5 D6 D7
SIN3
D0 D1 D2 D3 D4 D5 D6 D7
(2) When SM34 bit in S3C register = 1
CLK3
(NOTE 2)
SOUT3
D0 D1 D2 D3 D4 D5 D6 D7
SIN3
D0 D1 D2 D3 D4 D5 D6 D7
*This diagram applies to the case where the bits in the S3C register are set as follows:
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
NOTES:
1. When the SM36 bit = 1 (internal clock), a high level is output from the CLK3 pin if not
transferring data.
2. When the SM36 bit = 1 (internal clock), a low level is output from the CLK3 pin if not
transferring data.
Figure 15.39 Polarity of Transfer Clock
Rev.2.30 Oct 24, 2005 page 191 of 376
REJ09B0009-0230