M16C6N4 Datasheet, PDF(5/406 Page) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C6N4 Datasheet, PDF (5/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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Table of Contents

SFR Page Reference ............................................................................................................ B-1

1. Overview ............................................................................................................................... 1

1.1 Applications .................................................................................................................................................. 1

1.2 Performance Outline .................................................................................................................................... 2

1.3 Block Diagram .............................................................................................................................................. 3

1.4 Product List .................................................................................................................................................. 4

1.5 Pin Configuration ......................................................................................................................................... 5

1.6 Pin Description ............................................................................................................................................. 9

2. Central Processing Unit (CPU) ........................................................................................... 12

2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 12

2.2 Address Registers (A0 and A1) .................................................................................................................. 12

2.3 Frame Base Register (FB) ......................................................................................................................... 13

2.4 Interrupt Table Register (INTB) .................................................................................................................. 13

2.5 Program Counter (PC) ............................................................................................................................... 13

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ........................................................................... 13

2.7 Static Base Register (SB) .......................................................................................................................... 13

2.8 Flag Register (FLG) ................................................................................................................................... 13

2.8.1 Carry Flag (C Flag) ............................................................................................................................ 13

2.8.2 Debug Flag (D Flag) .......................................................................................................................... 13

2.8.3 Zero Flag (Z Flag) .............................................................................................................................. 13

2.8.4 Sign Flag (S Flag) .............................................................................................................................. 13

2.8.5 Register Bank Select Flag (B Flag) .................................................................................................... 13

2.8.6 Overflow Flag (O Flag) ....................................................................................................................... 13

2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................................. 13

2.8.8 Stack Pointer Select Flag (U Flag) ..................................................................................................... 13

2.8.9 Processor Interrupt Priority Level (IPL) .............................................................................................. 13

2.8.10 Reserved Area ................................................................................................................................. 13

3. Memory ............................................................................................................................... 14

4. Special Function Register (SFR) ......................................................................................... 15

5. Reset ................................................................................................................................... 31

5.1 Hardware Reset ......................................................................................................................................... 31

5.1.1 Reset on a Stable Supply Voltage ..................................................................................................... 31

5.1.2 Power-on Reset ................................................................................................................................. 31

5.2 Software Reset .......................................................................................................................................... 33

5.3 Watchdog Timer Reset ............................................................................................................................... 33

5.4 Oscillation Stop Detection Reset ............................................................................................................... 33

5.5 Internal Space ............................................................................................................................................ 33

6. Processor Mode .................................................................................................................. 34

6.1 Types of Processor Mode .......................................................................................................................... 34

6.2 Setting Processor Modes ........................................................................................................................... 34

7. Bus ...................................................................................................................................... 40

7.1 Bus Mode ................................................................................................................................................... 40

7.1.1 Separate Bus ..................................................................................................................................... 40

7.1.2 Multiplexed Bus .................................................................................................................................. 40

A-1

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