M16C6N4 Datasheet, PDF (402/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6N4) Hardware Manual
Rev. Date
2.10 Jun. 24, 2005
Page
238
240
242
284
285
286
2.30 Oct. 24, 2005 –
1
4
7, 8
9
31 to 33
33
44
51
57
58
59
60
63
64
67
70
Description
Summary
Figure 20.1 I/O Ports (1): “P7_0” in 4th figure is deleted.
Figure 20.3 I/O Ports (3): “P7_0” is added to middle figure.
Figure 20.6 I/O Pins: NOTE 1 is deleted.
Table 22.4 Electrical Characteristics (1)
• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.
Table 22.5 Electrical Characteristics (2): Mask ROM (5th item)
• “f(XCIN)” is changed to “(f(BCLK)).
Table 22.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
Revised edition issued
* Electric Characteristics of Normal-ver. is added.
* Revised parts and revised contents are as follows (except for expressional change).
1.1 Applications: Comment of Normal-ver. is added.
Table 1.2 Product List: NOTE 1 is added.
Tables 1.3 and 1.4 Pin Characteristics (1)(2) are added.
Table 1.5 Pin Description (1)
• 3.0 to 3.6 V (Normal-ver.) is added to Description of Power supply input.
5. Reset: Layout is changed.
5.5 Internal Space is added.
7.2.6 RDY Signal: Last sentence is revised.
Table 8.1 Clock Generating Circuit Specifications
• Clock Frequency in PLL Frequency Synthesizer: 24 MHz ⁽¹⁾ is added.
• NOTE 1 is added.
Figure 8.8 PLC0 Register
• PLC02 to PLC00 bits: Function of 011b is revised.
• NOTE 4 is added.
Figure 8.9 Examples of Main Clock Connection Circuit is revised.
Figure 8.10 Examples of Sub Clock Connection Circuit is revised.
8.1.4 PLL Clock
• 9th line: The sentence (When the PLL ... to) is added.
• 12th line: 24 MHz and NOTE 1 is added to PLL clock frequency.
• NOTE 1 is added.
Figure 8.2 Example for Setting PLL Clock Frequencies
• 24 MHz is added to PLL clock.
• 24 MHz is added to NOTE 1.
• NOTES 2 and 3 are added.
8.4.1.2 PLL Operation Mode
• 1st line: The main clock multiplied by “6” and NOTE 1 is added.
8.4.1.6 On-chip Oscillator Mode: Last sentence (When the operation mode is ...) is added.
8.4.1.7 On-chip Oscillator Low Power Dissipation Mode: Last sentence (When the
operation mode is ...) is deleted.
Table 8.6 Interrrupts to Stop Mode and Use Conditions is added.
Figure 8.13 State Transition in Normal Operation Mode: NOTE 7 is deleted.
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