M16C6N4 Datasheet, PDF (97/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
10. Interrupt
10.4.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector
table area. Table 10.2 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 10.2 Relocatable Vector Tables
Interrupt Source
Vector Address ⁽¹⁾
Address (L) to Address (H)
Software
Interrupt Number
Reference
BRK Instruction ⁽²⁾
+0 to +3 (0000h to 0003h)
0
M16C/60, M16C/20, M16C/Tiny
CAN0/1 Wake-up ⁽¹⁰⁾
+4 to +7 (0004h to 0007h)
Series Software Manual
1
19. CAN Module
CAN0 Successful Reception
+8 to +11 (0008h to 000Bh)
2
CAN0 Successful Transmission
________
INT3
+12 to +15 (000Ch to 000Fh)
+16 to +19 (0010h to 0013h)
3
______
4
10.6 INT Interrupt
Timer B5
+20 to +23 (0014h to 0017h)
Timer B4, UART1 Bus Collision Detection ^{(3) (9)} +24 to +27 (0018h to 001Bh)
Timer B3, UART0 Bus Collision Detection (4) (9) +28 to +31 (001Ch to 001Fh)
________
CAN1 Successful Reception,INT5 (5) +32 to +35 (0020h to 0023h)
________
SIO3, CAN1 Successful Transmission, INT4 ⁽⁶⁾ +36 to +39 (0024h to 0027h)
UART2 Bus Collision Detection ⁽⁹⁾
+40 to +43 (0028h to 002Bh)
5
13. Timers
6
13. Timers
7
15. Serial Interface
______
8
19. CAN Module, 10.6 INT Interrupt
______
9
15. Serial Interface, 19. CAN Module, 10.6 INT Interrupt
10
15. Serial Interface
DMA0
+44 to +47 (002Ch to 002Fh)
11
12. DMAC
DMA1
CAN0/1 Error ⁽¹¹⁾
A/D, Key Input ⁽⁷⁾
UART2 Transmission, NACK2 ⁽⁸⁾
UART2 Reception, ACK2 ⁽⁸⁾
UART0 Transmission, NACK0 ⁽⁸⁾
UART0 Reception, ACK0 ⁽⁸⁾
UART1 Transmission, NACK1 ⁽⁸⁾
UART1 Reception, ACK1 ⁽⁸⁾
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+60 to +63 (003Ch to 003Fh)
+64 to +67 (0040h to 0043h)
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+76 to +79 (004Ch to 004Fh)
+80 to +83 (0050h to 0053h)
12
13
19. CAN Module
14
16. A/D Convertor, 10.8 Key Input Interrupt
15
15. Serial Interface
16
17
18
19
20
Timer A0
+84 to +87 (0054h to 0057h)
21
13. Timers
Timer A1
+88 to +91 (0058h to 005Bh)
22
Timer A2
+92 to +95 (005Ch to 005Fh)
23
Timer A3
+96 to +99 (0060h to 0063h)
24
Timer A4
+100 to +103 (0064h to 0067h)
25
Timer B0
+104 to +107 (0068h to 006Bh)
26
Timer B1
+108 to +111 (006Ch to 006Fh)
27
Timer B2
________
INT0
________
INT1
________
INT2
INT Instruction Interrupt ⁽²⁾
+112 to +115 (0070h to 0073h)
28
______
+116 to +119 (0074h to 0077h)
29
10.6 INT Interrupt
+120 to +123 (0078h to 007Bh)
30
+124 to +127 (007Ch to 007Fh)
31
+128 to +131 (0080h to 0083h)
32
M16C/60, M16C/20, M16C/Tiny
to
to
Series Software Manual
+252 to + 255 (00FCh to 00FFh)
63
NOTES:
1. Address relative to address in INTB.
2. These interrupts cannot be disabled using the I flag.
3. Use the IFSR07 bit in the IFSR0 register to select.
4. Use the IFSR06 bit in the IFSR0 register to select.
5. Use the IFSR17 bit in the IFSR1 register to select.
6. Use the IFSR16 bit in the IFSR1 register to select.
Furthermore, use the IFSR00 bit in the IFSR0 register to select, when selecting SI/O3 or CAN1 successful transmission.
7. Use the IFSR01 bit in the IFSR0 register to select.
8. During I²C mode, NACK and ACK interrupts comprise the interrupt source.
9. Bus collision detection: During IE mode, this bus collision detection constitutes the cause of an interrupt.
During I²C mode, a start condition or a stop condition detection constitutes the cause of an interrupt.
10. Use the IFSR02 bit in the IFSR0 register to select. When the IFSR02 bit = 0, CAN0/1 wake-up is selected. When the
IFSR02 bit = 1, CAN0 wake-up/error is selected.
11. Use the IFSR02 bit in the IFSR0 register to select. When the IFSR02 bit = 0, CAN0/1 error is selected. When the IFSR02
bit = 1, CAN1 wake-up/error is selected.
Rev.2.30 Oct 24, 2005 page 79 of 376
REJ09B0009-0230