M16C6N4 Datasheet, PDF (400/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6N4) Hardware Manual
Rev. Date
Page
Description
Summary
2.00 Nov. 10, 2004 278 Figure 21.18 Pin Connections for CAN I/O Mode (2) is added.
280 Table 21.9 Flash Memory Version Electrical Characteristics
• Parameter is added and the value of some item is revised.
281 Table 22.1 Absolute Maximum Ratings
• "Flash Program Erase" in Operating Ambient Temperature is added.
283 Table 22.3 Recommended Operating Conditions (2)
• Parameters of Power Supply Ripple are added.
• NOTE 4 is revised.
Figure 22.1 Timing of Voltage Fluctuation is added.
284 Table 22.4 Electrical Characteristics (1): Hysteresis
• "CLK4" is revised to "CLK3", and "TA2OUT" is revised to "TA0OUT".
____________
• Max. of Standard in RESET is revised from "2.2" to "2.5".
• XIN is added.
286 Table 22.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added.
287 Table 22.8 Power Supply Circuit Timing Characteristics: "td(M-L)" is deleted.
Figure 22.2 Power Supply Circuit Timing Diagram is added.
288 Table 22.10 Memory Expansion Mode and Microprocessor Mode: "td(BCLK-HLDA)" is deleted.
290 Table 22.21 Serial I/O: Min. of standard in tsu(D-C) is revised from "30" to "70".
291 Table 22.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
• td(BCLK-HLDA) is added.
292 Table 22.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting
and external area access)
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
• td(BCLK-HLDA) is added.
293 Table 22.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting,
external area access and multiplexed bus selection)
• td(BCLK-HLDA) is added.
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
294 Figure 22.4 Timing Diagram (1): "XIN input" is added.
296, 297 Figures 22.6 and 22.7 Timing Diagram (3) (4): "DB" in Read timing is revised to "DBi".
298, 299 Figures 22.8 and 22.9 Timing Diagram (5) (6): "DB" in Write timing is revised to "DBi".
301 Figure 22.11 Timing Diagram (8)
• "ADi/DB" in Read/Write timing is revised to "ADi/DBi".
302 23.1 External Bus: The description of the external ROM version is deleted.
303 23.2 PLL Frequency Synthesizer is revised.
304 23.3 Power Control
• 2nd item is added. (Set the MR0 bit in the TAiMR register to •••)
• 4th item is revised. (Wait for main clock oscillation •••)
• Section of "External clock" is deleted.
316 23.8.2.1 Special Mode 1 (I²C Mode) is added.
317 23.8.3 SI/O3 is added.
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